Here is the abstract you requested from the RAMP_2016 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Challenges in packaging and assembly advanced power amplifiers|
|Keywords: packaging, die-mount, solder|
|Power amplifiers packaging and assembly have been quite different from the logic memory devices due to the large power dissipation from the device to the package body. Although conductive epoxy has been used for power amplifiers in low power range, high temperature solder bonding is the mainstream for packaging the high power devices towards the highest reliability. In order to reach better electrical and thermal performance, the thickness of power transistors has been reduced to less than 100 microns. As a result, more challenges associated with this change occurred in the fabrication and packaging of power devices. In this presentation, a number of challenges in the back-end fabrication process for RF power transistors including bipolar, GaAs, GaN and MMiC will be discussed. Some results of case study will be presented.|
|Cai Liang, Engineer
Integra Technologies inc.
El Segundo, CA