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System in Package Design: Performance-Based Partitioning and Placement
Keywords: system-in-package, thermal management, design
As the electronics industry progresses the most common prelude to a research paper is that products are getting smaller and much more compact, which drives design and integration at device, packaging, board and system levels. Moore’s law has guided the industry for decades, but as we all know, physics are limiting the year-over-year reduction in feature size and cost as manufacturing becomes more expensive and complex. This shifts much of the focus on higher performance and integration to the ‘back-end’ at the packaging level. Novel technologies have increased the density of packaged parts such as 2.5D, TSV, stacked chips and package level integration for basic functions dubbed ‘system-in-package’(SiP). The evolution of SiP is borne from what used to be called ‘hybrid’ and MCM packaging which in many cases used ceramic substrates, were hermetic and required a brazed lid. These packages still exist and are typically reserved for space and harsh environments. SiP designs range from simple functional blocks such as TX and RX modules for communications with few chips and passives to highly integrated systems capable of containing many functions in one package. One of the major differences in SiP as compared to MCM or hybrid is that SiP typically use non-hermetic packaging, organic or metal substrates with plastic overmold, and are aimed at consumer products as well as aerospace applications. SiP also utilizes stacked chips, which were used in MCM packaging rarely. With the advent of increasing internet connectivity (IoT), many of these products are aimed at personal use markets and most are small and thin. This work focuses on more complex SiP designs that include multiple chips and multiple passive components. The goal of the work is to introduce some of the challenges in designing a SiP with many components. One of the first challenges (after component selection) is to partition the design with performance-based metrics. Electrical and thermal performance parameters are the most common challenges in most products as well as mechanical and reliability. When considering electrical partitioning for multiple chips it is necessary to understand signal and power integrity requirements as well as the physical location of the passives with respect to the given chip. At the same time, thermal impact on layout must also be considered as a primary concern. Although each chip may not be high power, when the chips are combined in a small space thermal management becomes an issue which must be addressed at the beginning of the concept with component selection and operating temperature ranges for each chip. Just as with electrical performance demanding controlled impedance and matched line-lengths, thermal issues must be evaluated and juxtaposed against the electrical and physical constraints. This paper discusses design of a highly-integrated SiP product with emphasis on thermal analysis.
Thomas Tarter, President
Package Science Services LLC
Santa Clara, CA
USA


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