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Meeting High Performance Computing Signal and Power Integrity Requirements with Novel Technologies
Keywords: Signal/power integrity, Novel Technologies, High end Computing
Enhanced semiconductor processing, architecture and feature advances enabled significant performance advances in processor speed, integrated functionality and overall processor performance. These in turn drive increasing I/O counts (>10,000), decreasing bump pitch (<150 microns), lower core voltage (<0.85V), higher current loading (>100A), higher power dissipation (>150W), and faster switching times. At the same time, lead-free and RoHS international regulations are putting new restrictions on material selection with the inherent problems associated with lead free bumps and smaller pitch bumps such as susceptibility to electro-migration that packaging fabricators must provide mitigation means. Organic packaging fabricators are facing customer demands to provide finer line and space, smaller vias, with sequential build-up layers for semiconductor packages. Whereas low loss high speed interconnects with wide lines/space and large connectors are needed for high performance cards and boards. Packaging innovations are essential in meeting the conflicting requirements of compute system densification, demanding high speed switching performance with serious SI/PI challenges. In order to accomplish these goals, new materials such as polymers with ultra low dielectric loss, lower CTE, lower moisture up-take, higher Tg and lower dielectric constant have been developed. Novel interconnect structures, embedded capacitance layers and non-traditional PWB construction technologies leading to superior SI/PI performance have been successfully demonstrated recently and is discussed in this paper.
How T. Lin, CTO
ExSys Technology , inc
Endicott, NY

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