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|Panel Level Semiconductor Packaging Assembly Challenges|
|Keywords: Thin Die, System in Package, Panel Level fanout assembly|
|'Intelligence of Things', Mobile and Autonomous Vehicles are driving substantial growth in semiconductor requirements and unit volumes. Thinner formfactor's, increasing bandwidth, and heterogeneous integration are creating significant demands for advanced semiconductor packaging solutions. Thin formfactors require thinner die and thinner substrate solutions. Increasing bandwidth is driving higher IO density and finer pitch Line/Space circuit routing geometries. Heterogeneous integration creates a mix of multiple die types in the same package. One approach that appears to offer great promise to meet these challenges is Panel Level Fanout assembly. The move to Panel Level results in a multitude of technical and business issues to be addressed. Achieving high accuracy placement over work areas greater than 600mm x 600mm, while maintaining this accuracy in a high volume manufacturing environment, is critical. Achieving high utilization when placing multiple die types is also essential. In this paper we will explore these issues from the perspective of establishing an economic, high yield pick and place solution. We will consider the process aspects impacting accuracy, and the system requirements to enable the roadmap for Fan Out applications. The challenges of handling thin die will be explored, and approaches to address these will be highlighted. System in Package (SiP), with a mix of multiple die types and passives, will be assessed and key issues such as how to identify who owns yield loss due to bad die will be addressed.|
|Glenn Farris, Vice President