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|Power Si/SiC LDMOSFET for harsh space applications|
|Keywords: Si on SiC, Radiation, LDMOSFET|
|Electronic devices that are able to work efficiently and reliably at harsh environments (e.g. huge temperature difference, high radiation) are required for space applications. Recently there has been a drive for space power electronics to move to high voltage transmission, beyond the 120 V maximum used today. This would allow harness weight, which can be up to 10% of satellite weight, to be greatly reduced given the reduction in large Ohmic resistance (l2R) losses . While SiC is considered as the next generation power electronics semiconductors, integration of full SiC solutions that include switching devices such as MOSFETs are still held back by problems with long term reliability, stability and packaging. As a consequence, it can be expected that Si and SOI devices will continue dominating the space market for the near future. By confining the active area of the device, SOI devices achieve low leakage at high temperature . SOI is often the rad- hard choice at low voltage too, the small volume of active material leading to excellent single event immunity . However, a thick buried- oxide, which is required to support high voltage devices, make SOI devices much more sensitive to total ionizing dose (TID) effects. Our previous simulation results demonstrated that with a junction-to-case temperature 4 x less than Si , power transistors with breakdown voltage up to 600 V are achievable on Si/SiC substrates . The silicon-on-silicon carbide (Si/SiC) semiconductor substrate can improve upon SOI technology by using a semi-insulating SiC substrate to replace the buried oxide (BOX) layer which currently prevents efficient heat removal and causes poor TID tolerance. In this paper we, for the first time, demonstrate the electrical and radiation performance of a power LDMOSFET based on Si/SiC substrates. The 4 inch Si/SiC wafers were prepared by IceMOS Technology Ltd and the bonding process details are published elsewhere . 1 μm and 2 μm n-type Si device layers are lightly doped (5-45 Ω.cm) and bonded to the 300 μm thick on-axis semi-insulating (≥1.1e7 Ω.cm) 4H-SiC substrate. TEM was used to characterize the as-bonded Si/SiC interface and it was found out that in some areas a perfectly homogeneous interface was obtained, while in some other places features of pits or voids are seen, which may cause charge trapping and Fermi-level pinning there. We previously found that MOS capacitors fabricated on these as- bonded n-type Si layers showed p-type behaviour and it was suspected that a high density of interfacial charge caused band bending, which in such a thin, lightly doped Si layer inverts the doping polarity of the entire layer . As such, phosphorous was ion implantation and thermally diffused into as-bonded Si/SiC wafer surface to obtain an initial Si layer n-type doping of around 2e15 cm-3. Field plate and RESURF features were integrated into the device structure targeting 200-600 V blocking voltages. The electrical and radiation properties of the fabricated device are being carried out through experiments and simulations and the full results will be presented in the final paper.|
School of Engineering, University of Warwick
Coventry, West Midland