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A High-Temperature Standard Cell Library for Synthesis of Very Large Scale Integrated SiC CMOS Circuits
Keywords: SiC, CMOS, Synthesis
A high-fidelity PDK[1] of the HiTSiC® CMOS process[2] has been used to design a high-density standard cell logic library. The standard cell library contains all the necessary file formats to support fully automated logic synthesis with open-source Electronic Design Automation (EDA) software. Register-Transfer-Logic (RTL) is synthesized to a gate level design. The result is high-density circuit layouts that can operate above 250 ºC. The logic cells require a 12 V to 15 V supply and therefore are ideally suited for automotive and aerospace systems. Digital simulation models of each logic cell are extracted across process corners, supply voltage, and temperature (PVT) and parameterized for path delays, timing checks, and power domain assertions to comprise a response surface for each synthesized design. These extracted cell models are used for functional verification and timing closure with a digital simulator. As a final verification step, the physical design is extracted at the transistor level with interconnect parasitic elements and simulated in SPICE over PVT. Consequently, the library supports synthesis of logic functions for optimized performance for a nominal temperature (TNOM) ranging from 0 ºC to 470 ºC (Venus surface). Several high- temperature synthesized design examples will be presented including the finite state machine (FSM) controller for multi-channel analog-to-digital converter. Note: HiTSiC® CMOS is a Registered Trademark of Raytheon Systems, Ltd.
James A. Holmes, CTO
Ozark Integrated Circuits, Inc.
Fayetteville, AR
United States


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