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A 2 V to 15 V BiCMOS Level-Shifting Logic-Input Cell for SiC CMOS Integrated Circuits
Keywords: SiC, BiCMOS, Interface
The HiTSiC® CMOS process[1] provides high density logic for digital integrated circuit applications that operate above 250 ºC. The process provides complimentary N-channel and P- channel field effect transistors with threshold voltages of approximately 2.25 V. Consequently, the CMOS logic operates with supply voltage of 12 V to 15 volts, which is ideal for automotive and aerospace electronics that must operate in high-temperature domains such as those heated by internal combustion engines and jet engines. Operating HiTSiC® CMOS integrated circuits at 12 V and in a high- temperature domain presents a practical barrier to interfacing with electronics operating at lower power supply voltages (2 V to 5 V) and lower temperature domains (0 ºC to 125 ºC). To bridge the voltage and temperature domains, a BiCMOS digital level shifter was designed with the HiTSiC® CMOS process, then fabricated and tested from 25 ºC to 500 ºC. The level shifter is implemented with the parasitic NPN transistor formed in the NFET P-Type well[2]. An open emitter input configuration activates level translation from 2 V to 15 V through a CMOS buffer. This level shifter is one of many IO cells comprising a “perimeter” library that is described herein. The perimeter library is used to synthesize the pad frame for any 12 V SiC CMOS integrated circuit logic core. Note: HiTSiC® CMOS is a Registered Trademark of Raytheon Systems, Ltd.
James A. Holmes, CTO
Ozark Integrated Circuits, Inc.
Fayetteville, AR
United States

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