KESTER

Abstract Preview

Here is the abstract you requested from the HITEN_2017 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.

Comparison of a current mode reference generator versus a ΔVbe bandgap circuit in a 1.0m PD-SOI CMOS process for high temperature (225⁰C) environments.
Keywords: comparison, reference, generator
Both a traditional Vbe based bandgap and a novel current mode based voltage reference generator were designed, fabricated and tested on the same ASIC. The current-mode reference generator allows the traditional bandgap reference potential, typically 1.25V, to be scaled by the ratio of two resistors and therefore can notionally achieve any value [1]. The circuits were fabricated in a high- temperature 1.0 m partially-depleted silicon-on-insulator CMOS process, which can operate at temperatures of up to 300C. Initial testing of the fabricated chip has shown the current- mode reference potential to be 1.33V at 25C with a temperature coefficient 66 ppm/C relative to 120C. The bandgap circuit has an output of 1.22V at 25C and a temperature coefficient of 85 ppm/C, again relative to 120C. Simulation of the these circuits over process, temperature and supply predicted an output of 1.25V with a TC of 40 ppm/C for the current-mode reference and 1.18V with a TC of 43 ppm/C for the bandgap. Testing of the device has been performed over a temperature range of 25C to 260C. Component matching is critical to reduce the part-to-part variation of the reference voltage and its temperature coefficient. Mismatch is typically minimized by using large- area devices and common-centroid layouts. The design and layout of these circuits was especially challenging due to the high- temperature interconnect metal (tungsten) which exhibits a sheet resistance that is 4 times greater than the standard metal interconnect; 400m/ with the worst-case process corner at 1000m/. The common- centroid layout schemes were significantly more difficult to optimize since the long interconnect distances resulted in much higher parasitic metal resistances as a total proportion of the targeted layout impedance. Consequently, a block-level common centroid approach was adopted. Additional design challenges included the startup circuit for both reference generator circuits due to the wide operating temperature range (design: -55C to 300C). A drawback of the current mode architecture is an increase in complexity and die area. For the implementations employed here, the current-mode reference generator occupied an area of approximately 0.8mm2 whereas the bandgap circuit consumed 0.6mm2. Estimated current consumption was also higher for the current-mode reference versus the bandgap, 132 A and 49 A. It should be noted that neither system was optimized for space or power in this effort. Back-end processing of the ASIC was designed to allow for operation up to 300C. This included over-pad metallization of Ni/Pd/Au on the aluminum wire bond pads to prevent diffusion and subsequent formation of Kirkendall voids. Packaging and PCB processing were done with a continuous operational target of 225C. The device was packaged in a ceramic pin- grid array using a cyanate ester die attach. Gold wire was used for the wire bonds with gold flash metallization at the package lead frame. A polyimide PCB substrate with Tg250C was selected and a high melting point solder (Pb93.5Sn5Ag1.5) for component attach.
Alex Pike, Principle Electrical Engineer
Meggitt Sensing Systems
Irvine, CA
USA


CORPORATE PREMIER MEMBERS
  • Amkor
  • ASE
  • Canon
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • NGK NTK
  • Palomar
  • Plexus
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Specialty Coating Systems