Here is the abstract you requested from the Thermal_2017 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Thermal Reliability across Chip, Package, Board, and System Scales|
|Keywords: simulation, electro-thermal, thermal-mechanical|
|Thermal management plays a critical role in electronics reliability. This is true at the chip, package, board and system levels. Heat transfer at the chip level has a thermal impact at the other levels, and vice versa. Complicating matters are the complexity of an integrated circuit, as well as the package and printed circuit board (PCB) layout structures. How does one incorporate the geometric complexity of these structures as well as the spatially varying and temperature-dependent heat generation into a system-level thermal model that can be efficiently solved with a high level of accuracy? Moreover, how can one use the thermal information obtained to accurately evaluate electromigration (EM) in the chip, electrical resistive losses in the board, and thermal-structural failure in the package solder balls and the PCB? This presentation will aim to answer these questions by presenting an integrated simulation solution. To demonstrate the simulation process, an example will be shown. Here, a chip thermal model (CTM) is placed onto a detailed package in a system-level thermal model. The package is placed onto a PCB, which incorporates detailed joule heating. The board assembly is placed into a larger thermal system where both active and passive cooling mechanisms are employed. A coupled electro-thermal simulation is performed to determine temperatures throughout the system level model as well as currents/voltages within the PCB. Thermal boundary conditions on the IC package are returned to a chip-level tool to assess thermal-aware EM effects. Temperature maps are sent to a structural simulation tool to assess thermal-deformations. This presentation will demonstrate that modeling the coupled electrical, thermal, and thermal-induced stresses that exist at the chip, package, board and system levels is key to ensuring product thermal reliability.|
|David Geb, Application Engineer
Berkeley , CA