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|Fan-Out Wafer-Level-Packaging: Market and Technology Trends|
|Keywords: Fan-Out, FOWLP, Panel|
|The semiconductor industry is breaking records this year and expectations are high for the market future. In this context, advanced packaging importance will become more and more preponderant, considering scaling and cost reduction will not be possible just by continuing on the path the industry followed for the past few decades with Moore’s law. Advanced nodes do not bring the desired cost benefit anymore and R&D investments in new lithography solutions and devices below 10nm nodes are rising substantially. In order to answer market demands, the industry seeks further performance and functionality boosts in integration. Packages are now requested to bridge the gap and revive the cost/performance curve while at the same time adding more functionality through integration. They become enablers for new designs, new performances and new applications. In this work we will focus on Fan-Out packaging, an embedded package that dragged lots of interest for more than two years. The principle of Fan-Out technology is to embed products in a mold compound and allow redistribution layer pitch to be independent from die size. This approach is already mature for several years thanks to high volume products claimed by Nanium (part of Amkor since beginning of 2017) and JCET/Stats ChipPAC using eWLB type of Fan-Out but has seen a real evolution since the appearance of an aggressive technology from TSMC to package Apple’s APE. Fan-Out packaging comfort zone used to be low IO counts mobile applications such as baseband, PMIC/PMU and RF but its potential for larger IO counts applications and other markets has been demonstrated since then. In 2016, TSMC’s FOWLP solution called InFO was used to package Apple A10 application processor implemented in the IPhone 7. It created a huge interest for the platform and proved its capability to address complex applications at large volume. This trend was later confirmed by Apple, choosing again InFO for its next application processor, A11, in 2017. Fan-Out market is already representing a large value ($873M in 2017) and among it high-density fan-out applications market is more than $500M large. This could reach more than $1B in the coming years if other telecom players than Apple are willing to switch to Fan-Out packaging, which is expected. With such a buzz around Fan-Out packaging and understanding the potential of that market and the high demand from telecom industry for a thin and cheap package, capable of embedding complex ICs, other important manufacturers than TSMC are willing to enter the game with their own technologies but with different strategies. OSATs such as Amkor and ASE are offering new solutions such as Chip-last Fan-Out or Fan-Out on substrate to target other high-density applications than APE and enlarge Fan- Out market. Other players are willing to compete Nanium, STATS ChipPAC and ASE on the low-end market and get some of this large volume area. Some suppliers are also promoting Fan-Out potential in other markets than telecom such as NEPES for automotive and its offer for radars. Fan-Out market is getting more and more diversified. As a consequence, many technologies available in the field are marketed as “Fan-Out” while being very different to each other. There are even technologies that shall not be considered as Fan-Out packaging labeled as such. In order to not get lost in this offer maze, a clear segmentation and clear definitions are presented in this work. Along with detailed roadmaps and supply chain analysis, explaining the complexity and the trends already showing potential in this highly promising market, this work also provides manufacturing challenge analysis. The main parameter of interest being always the same in manufacturing: the cost. Main trend in Fan-Out packaging investigated at the moment to put down the cost is carrier size evolution and many manufacturers are considering that option. NEPES already announced its production capability of Fan-Out on panel and numerous players such as ASE are working hard to make that option available soon and get market shares. As package price represents the final verdict, carrier size evolution is an important topic. Moving fabrication from wafers to panels could help to reduce drastically the cost but represents high technical and financial challenges though. Panel Fan-Out still being at its early stage, lots of different solutions are investigated to build up cost- efficient lines: Types of panel (PCB, LCD, etc…) and sizes available are not standardized yet and many development are ongoing. Lots of challenges are ahead with yield, warpage, financial sustainability, etc… This work analyzes and explains status of the different players involved in panel manufacturing for Fan-Out. Overall, the presentation will provide an overview of the products announcements, commercialization roadmaps as well as market forecasts per application. Insights and trends into the different fan-out packaging approaches by applications, business models and major players will be reviewed.|