Honeywell

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Underfill dispensing for chip-on-wafer
Keywords: underfill, dispensing, chip-on-wafer
Underfill dispensing for chip-on-wafer The chip-on-wafer process is becoming a critical one in semiconductor assembly along with the rapid emergence of 3D package, stacked wafer level CSP (WLCSP), and chip-last process for WLCSP. A chip-on-wafer process involves placing multiple chips on a wafer, providing proper interconnections by bumps, adhesion by underfill between the chips and wafer, molding them if necessary before ball placement on the backside, and dicing. The chips are the molded components in the case of stacked WLCSP, and the wafer is either a silicon wafer/interposer, a molded wafer, a coreless substrate, or redistributed layers (RDL). In semiconductor packaging, the demands for cost reduction and miniaturization challenge the chip-on- wafer process exponentially. For example, the scribe line width (horizontal space between chips) on wafer and interconnect gap between chip and wafer are becoming tighter. These tighter geometries make underfill dispensing very time consuming due to the need for smaller dot mass and jetted stream width, thereby requiring multiple passes to effectively underfill the die. In addition, the tighter geometries increase the need for high accuracy in terms of both placement and volume. All of these factors are critically important because of the high value of the wafer and the reality that a single yield issue can affect hundreds of chips. This paper will address these challenges and how they can be solved by newly developed dispensing technology solutions. Examples from the field include: A faster jet cycle saved significant production time. Conditions: 10 ug of fluid material was dispensed by a jet; 50 mg underfill per chip; 300 chips per wafer and the jetting at 200-Hz frequency. (300 x 50,000)/(10 x 200) = 7,500 sec or more than 2 hours to underfill chips on one wafer. A newly developed jet dispenser decreased the cycle time down to just 40 minutes by increasing the jet frequency to 600 Hz. Another example involved a wafer where the target space between two chips was only a few hundred micrometers. The combination of jetted stream width, x-y placement accuracy, and dot volume variation all have to fit within this narrow space. A newly developed dispenser and platform dispensed small dots into the space for underfilling. Actual field data tested a new jet design that has a much longer lifetime. Assuming a jet dispenser life expectancy of 500 million cycles and a wafer application requiring 1 million jet cycles to complete, the failure rate could be 1/500th = 0.2%. A new jetting technology has an extended life expectancy of 2 billion cycles, reducing the failure rate to 0.05%. This improvement has a significantly positive impact on the cost to produce each wafer. The newly developed technology and products thus successfully solved the challenges that the chip-on-wafer process is facing now. And these technology and products are applicable to all of the emerging packaging technologies such as 3D package, stacked wafer level CSP (WLCSP), and chip-last process for WLCSP.
Akira Morita,
Nordson Asymtek
Carlsbad, CA
United States


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