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|Design, Characterization and Testing of Large-area and High-density 3D Interconnection by Direct Bond Interconnect|
|Keywords: 3D IC, high density, hybrid bond interconnect|
|High-bandwidth and low power data access in electronic applications requires vertical stacking of semiconductor chips with very fine pitch interconnects between the stacked layers. In recent years, a unique technology referred to as Direct Bond Interconnect (DBI) was implemented in CMOS image sensor manufacturing to obtain enhanced performance. Wafer to wafer (W2W) bonding with peripheral thru-via interconnects is commercialized in CMOS image sensors for interconnection with IC. DBI bonding in W2W form is able to integrate CMOS image sensor chips with memory and data processing chips through 3D interconnect at the pixel level (with very high density) to achieve high-speed and high- definition video capability demanded by high-end applications in mobile, Virtual Reality (VR), Augmented Reality (AR) and Internet of Things (IoT) markets . The hybrid bonding technology aligns dielectric and metal interconnect regions on each wafer (or die) to the corresponding dielectric and metal interconnect regions on the opposite wafers and bonds at room temperature. The room- temperature bond provides mechanical support until Direct Cu-Cu bonding completes in a batch anneal process and consequently the dense electrical interconnects between the two devices are joined at higher temperatures. The result is a stacked Si module with only inorganic layers between the devices. In fact, no under-bump metallurgy (UBM), under-fill material or micro-bumps are present. The instantaneous, room-temperature bonding enables high throughput bonding, critical for high-volume and low-cost manufacturing. This scalable technology enables semiconductor manufacturers to offer high performance, low power silicon modules for electronics in a broad range of applications including mobile, wearable, sensors, data centers and telecommunication. Multiple test vehicles are studied to measure the electrical connectivity yield and reliability of 3D interconnects formed by the Cu-Cu DBI joints using various daisy chain designs with different bond pad size, pitch and chain length. The daisy chain structures consist of face-to- face bonded DBI joints and the complimentary half chain structures on the paired chips to complete the daisy chain. All test vehicles are assembled with either W2W or Die-to-Wafer (D2W) processes. Examples of our W2W test vehicle, include a single daisy chain composed of >700k DBI links at 4um pitch covers the full bonding area of 3.16mm X 3.68mm and in another design of higher density, one chain of > 2 million DBI links at 2um pitch covers the same area. The D2W assembly approach is essential for employing known-good-dies and integrating dies of varying sizes from different manufacturing lines. In order to develop high-yield and high-throughput D2W process , multiple daisy chains have been designed at different locations of a die to evaluate the bonding quality in the corner, edge and central regions with the longest daisy chain of >30k DBI links at 10um pitch covering a bonding area of 5.36mm X 9.36mm. This paper discusses the electrical test result of the daisy chains upon bonding, metrology characterization to estimate bonding quality. Furthermore reliability tests were conducted over the test vehicles, including thermal shock, autoclave, Temperature Cycle Test (TCT), High Temperature Storage (HTS) and Moisture Sensitivity Level (MSL) tests. A single DBI test structure resistance, excluding probe contact resistance, is extracted from electrical measurements from a series of chain lengths. The electrical resistance is close to the calculated value indicating very small misalignment during DBI bonding process which is verified by infrared imaging. Non-destructive imaging techniques (acoustic or infrared imaging) as well as cross-sectional imaging show the bond interface quality. Visible defects shown in the acoustic images correspond to the locations of the out-of-spec daisy chain resistance in electrical measurement. The flatness of sample surface, roughness of oxide and recess of copper in the DBI pattern were measured with atomic force microscopy. The average recess depth of copper of DBI pad before bonding tracks with the yield of the electrical test after bonding.|
|Liang Wang, Sr. Manager of R&D Engineering
San Jose, CA