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Advancement of Fine Pitch Interconnect Technology
Keywords: fine pitch, flipchip, interconnect
Advanced semiconductor packaging requirements for higher and faster performance in a thinner and smaller form factor continues to grow for mobile, network and consumer devices. While the increase in device input/output (I/O) density is driven by the famous “Moore’s Law”, the packaging industry is experiencing opposing trends for more complex packaging solutions while the expected cost targets are in a downward trend. Packaging technology has become more challenging and complicated than ever before, driving advanced silicon (Si) nodes, finer bump pitch as well as finer line width and spacing substrate manufacturing capabilities to satisfy the increasing requirements in the semiconductor industry. As increasing input/output (I/O) counts in a package are needed in mobile devices, packaging solutions are migrating from traditional wire bond packages to flip chip interconnect to meet these requirements. Flip chip chip scale package (fcCSP) is viewed as an attractive solution for complicated and highly integrated systems with multiple functions and heterogeneous mobile applications. Although emerging markets are driving advanced technologies in high performance mobile devices, assembly cost is still the major concern to be addressed. Due to the rapid growth in emerging markets for mobile applications, advanced Si node technology development with fine flip chip bump pitch for mobile applications is widely viewed as a way to pursue the die size reduction, efficiency enhancement and lower power consumption in the device. Today flip chip bump pitches are reduced to as low as 60µm pitch. Risk for package assembly with traditional mass reflow (MR) is much higher than ever before. To address these kinds of issues and to simplify the manufacturing processes for the next generation fine pitch flip chip, thermal compression bonding (TCB) or thermal compression with non-conductive paste (TCNCP) was introduced into the assembly process. Each process has some merits and demerits. Another new technology very recently introduced in the market for fine pitch bump interconnection is called laser assisted bonding (LAB). In this technology an infra-red (IR) laser is used to heat up the entire die only and make a good interconnection joint between the die to substrate and enhance overall throughput much better than TCNCP. This paper will addresses various risk factors for fine bump pitch flip chip assembly, risk mitigation plan; comprehensive assembly and reliability data as well some cost benchmarking.
Nokibul Islam,
StatsChipPAC Inc
Fremont, CA
USA


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