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Heterogeneous Integration: Are your design tools and methodologies up to the task?
Keywords: Heterogenous Integration, SiP, Design Tools
Gordon Moore, famously predicted a trajectory in which the transistor count of IC’s would double every two years driving transistor cost on a constant downward path. This prediction later came to be known as Moore’s Law. For the past several decades, the electronics industry has thrived while enjoying the benefits of Moore’s Law. It’s been a great run. However, due to the tremendous costs associated with designing a chip at the latest node - along with other factors – companies have begun to look for design alternatives. Many of these companies are looking at advanced, multi-die IC packaging technologies to solve the next generation of design challenges. The term that is often used to describe this design trend is “heterogeneous integration”. Heterogeneous integration is not entirely new to the packaging community. However, the latest technologies and design requirements are likely going to stress existing MCM/SiP design teams. Tighter communication between IC and package design teams is a given for the next generation of multi-die packages. But, is better communication across design teams enough? Probably not. A new set of requirements, mostly driven from the IC designer’s perspective is coming with the next generation of designs. These requirements may include layout vs. schematic (LVS) checks, timing sign-off, silicon substrates and others. The bottom line is, new design tools and methodologies will likely be required. This presentation will provide an overview of the latest trends in heterogeneous integration. And, outline some of the design tool/flow challenges that will need to be addressed to design the next generation of multi-die packages.
John Park, Product Managment Director
Cadence Design Systems
San Jose, CA

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