Honeywell

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Embedded Wafer Level Ball Grid Array as One Solution for 2.5D System in Package
Keywords: System in Package, Fan Out, Design
Today’s millenial consumers are looking for powerful, multi-functional electronic devies with unprecdented performance and speed, yet small, thin and low cost. This requirement, coupled with a growing awareness of a more holistic system configuration has continued to drive innovations in System in Package (SiP) solutions. System-in-Package (SiP) is a functional electronic system or sub-system that combines two or more heterogeneous die ( often with different technology nodes) which may include passive components and/or MEMs assembled into a module with a combination of wirebond and/or flip chip onto a substrate which is then overmolded. The disruptive technology where embedded Wafer Level Ball Grid Array ( eWLB ) Fan Out comes in is replacing the need for a laminate substrate for an SiP. This paper will present a case study of integrating multiple die with several passive components into an eWLB-SiP.We will review the design guidelines for high density redistribution lines (RDL) from die to die where fine line width and line spacing are fabricated and implemented on the eWLB platform. We will also review die to mold aspect ratio and how it relates to warpage on eWLB Fan Out and design considerations for multiple die eWLB-SiP. Successful reliability and electrical characterization results on multi die eWLB-SiP are reported as an enabling technology for highly integrated, miniaturized, low profile and cost effective solutions.
Jacinta Aman Lim,
STATS ChipPAC
Fremont, CA
USA


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