Here is the abstract you requested from the dpc_2018 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|3d die stacks w/o TSVs that operate at comparable high bandwidth and power efficiency|
|Keywords: 3d die stacks, high bandwidth and power efficiency, no TSVs to reduce packaging cost|
|The application of TSV based die stacks for Processor - Memory modules requiring high bandwidth and low power to transmit data through the interconnects have not yet taken off for consumer applications. The high cost of this latest packaging technology arises from the large number of TSVs required on die ( approx. 5,000 for DRAM chips ), manufacturing throughput limited by the slow & sequential process of thermo - compression flip chip bonding being used so far to build 3d stacks with 4 or more dies, yield losses etc. As a result only high margin, High Performance Computing can afford to use 3d memory stacks employing TSVs. Even relatively high margin consumer applications such as Game Modules ( the first application where TSV based memory stacks were first tried ) have not taken off and for Consumer systems with similar price - performance characteristics such as guidance system for self driven cars an alternative to TSV based stacks is needed. TSVs are a very mechanical solution to an electrical problem i.e. reduce the interconnect parasitics by shortening them. However such shortening brings with them thermo - physical incompatibilities and stresses and this is exhibited in case of TSVs with the need to maintain Keep Out Zones and the consequent loss of die real estate. In this paper we present an alternative approach to reduce interconnect parasitics and their application to build die stacks w/o TSVs. Key features of both design and process will be discussed.|
|Dev Gupta, CTO