Here is the abstract you requested from the dpc_2018 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Moving from Wafer Level Packaging to Panel Format|
|Keywords: Fan-Out Packaging, redistribution layer (RDL), Tall Pillar|
|In the past few years there was a shift away from single PCs to more connected devices like smartphones or wearables. Worldwide population may slightly grow in the future (up to 9.7 billion in 2050), but the number of devices will grow much faster and they will be much smarter. This means we will need more complex devices at same real estate and lower costs. To meet the challenges of this “More than Moore” trend new solutions have to be found. Fan-Out Wafer Level Packaging (FO-WLP) was introduced some years ago and many industry analysts now see it as a key advanced packaging platform to meet the technological and cost requirements of the industry. The sizes for these substrates increased over the past years and now substrates larger than 300 mm are the next step to take advantages in economies of scale in the manufacturing processes. Since the successful implementation of Fan-Out Wafer Level Packaging (FO-WLP) in the production of the iPhone 7 the industry has proven that Fan-out packaging can be used at reasonable costs in mass production. Many players are now interested to increase the through-put and lower the total cost by moving from round wafers to panel format. The move from round to square substrates increases the effective area and allows even more dies to be produced in order to further reduce costs. This currently drives the industry and the supply chain - the transfer of FO-WLP to FO-PLP (Fan-Out Panel Level Packaging) and this requires the development of new products and solutions. This transfer will offer new possibilities but it also raises challenges. Nowadays customers are targeting for sizes even larger than the commonly used printed circuit boards (PCB) panel formats like 510 × 515 mm² or 458 × 610 mm². The processing of large scale substrates at high yield and low costs is a tremendous challenge for the semiconductor packaging industry and its supply chain. Substrate manufacturers looking for using their existing infrastructure and experience in handling of square formats, however adjustments have to me made for handling and processing of these formats while meeting the requirement of excellent surface distribution to meet the yield targets. In addition increasing technical requirements like L/S resolution down to 2 µm and high plating uniformity on large areas place extreme high demands on materials and processing equipment. In this paper we are describing the concept of a plating tool called MultiPlate®. Based on years of in-house experience this tool was introduced for fabrication of wafers in 2013 and for panel formats up to 510 × 515 mm² in 2016. This year the latest version was installed for detailed investigations, allowing for processing of panel sizes up to 650 × 600 mm. This paper also describes the latest performance of newly developed electrolytes for high speed Cu deposition in RDL layer plating with and without micro vias as well as tall pillar plating (PoP design). We will focus on FO-PLP and will address a major challenge, which is the Cu distribution over the panel for various panel formats (370 × 470 mm² up to 600 × 600 mm²). Other requirements for both applications are process stability and feature shape, the latter can be adjusted by equipment features without usage of strong levellers. The absence of strong Levellers leads to less co-deposition and fewer voids. The article will show the improvements achieved during the past two years by using our concept of parallel optimisation of plating tool, physical parameters (e.g.: electrolyte flow, current density and reverse pulse plating) and electrolyte settings. The plated copper deposits show excellent physical properties when plated at high current densities and the system allows for deposition of highly pure copper which leads to higher throughput, lower voiding and better reliability. A lot of progress has been made in terms of the major challenge uniformity, which is being judged by the so called WithIn-Unit Distribution (WIUD) as it is also a prerequisite of achieving a high yield during production. We can show that good distribution can be achieved at high current densities by using the right plating tool and electrolyte adjustments. We believe that this combination is the answer for the challenges the industry currently faces. Our investigation shows that equipment infrastructure and process are scalable to panel format. FO-PLP is ready for the next step and has the potential to be a strong competition for WLP for the coming years. Our main concern lies in another part of this technology shift. Working together with many cooperation partners we see the main challenge in standardization of panel formats. The industry is still experimenting a lot with different formats and sizes but has to agree to a common standard to achieve the cost saving potential promised by this technology.|
|Henning Hübner, Global Product Manager
Atotech Deutschland GmbH