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2018 A TURNING POINT FOR 3D TSV INTEGRATION: WILL AI BE THE REAL OPPORTUNITY FOR 3D AND 2.5D INTEGRATION?
Keywords: 3D integration, Artificial Intelligence, High Performance Computing
Semiconductor industry, for more than four decades, has rigorously followed Moore’s Law in scaling down the CMOS technologies. The industry is looking for technology solutions combining performance, integration and cost not limited to the CMOS scaling. The semiconductor industry’s hopes and patience were rewarded a few years ago when three-dimensional (3D) stacked devices have entered the market using vertical interconnect Through-Silicon Vias (TSV). Since their introduction, TSVs have held designers’ attention since the performance potential offered by this technology is unequalled by any other packaging platform today. Initially introduced in MEMS technology and then in imaging, TSVs have thereafter enabled tremendous performance in high-end products. Artificial Intelligence (AI) will be more present in the future in consumers, automotive, medical and also industrial applications. The change that occurs in semiconductor industry is to be considered a new opportunity for silicon makers as emerging needs such as deep learning brought out more challenges to the IC but also to the packaging industry. 3D integration fits well AI and High-Performance Computing (HPC) products requirements, as it offers low-power consumption with capacity to transfer large quantity of data at low latency. Major players have launched a certain number of products offering unequalled performance based on CPU, GPU and FPGA devices. This presentation will make a status of available commercial products based on 3D integration dedicated to high-end performance including deep learning and HPC and discuss the next-gen products. With a potential of more than 700 000 TSV-based wafers by 2022 for high-end products, the 3D integrated high-end products have a revenues Compound Annual Growth Rate (CAGR) of 27%. Driven by 3D stacked memories, High-Bandwidth Memory (HBM) product is knowing a large success and became a standard memory up to eight memory die stacks and on top of datacenters and supercomputers, HBM is likely to be implemented in vehicles and Augmented Reality (AR) headsets. Smart integration can also consist in partitioning dies, and connecting them or in two and a half dimensional platform (2.5D) through an interposer or in 3D as 3D System-On-Chip (3D SoC). The 2.5D solution is targeted for standardizing, improving yield, and enabling heterogeneous integration. Silicon interposer has enabled high-density integration for customized dies. The 3D partitioning consists in stacking vertically two dies interconnected through TSV by fusion or hybrid bonding. Some alternative packaging technologies (TSV-less) have emerged like the EMbedded Interconnect Bridge (EMIB) solution from Intel, but also high-density Fan-Out Wafer Level Packaging (FO-WLP) developed by several OSATs. Even though a consolidated supply chain was built from interactions between foundries, OSATS and module makers, this presentation will also discuss the change that occurs in semiconductor supply chain and specifically the business models move. While web companies are positioning downstream in the supply chain to gain better control over outsourcing IC manufacturing and assembly, as well as gain higher shares in the value chain, “traditional” chip makers are moving upwards, like Nvidia, which launched a server product based on its GPU Tesla P100/V100 for deep-learning applications.
Emilie JOLIVET, Market and Technology analyst
YOLE DEVELOPPEMENT
Villeurbanne, RA
FRANCE


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