Here is the abstract you requested from the dpc_2018 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Managing Intra-Package Impedance Discontinuities with Printed Interconnects|
|Keywords: Impedance discontinuites, Printed interconnect, Aerosol Jet|
|The abstract has 8 figures that don't show up here. I can send a pdf if needed. Impedance Discontinuities With operating frequencies often exceeding 1 GHz, even digital designers must now apply RF lumped and distributed models to their designs. PCB, PCB-package and on-chip conductors are now optimized to minimize impedance discontinuities, leaving the internal package-to-die and die-to-die wire-bond interconnects as the primary signal integrity issue. While designers can employ matching networks to efficiently couple narrow-band RF signals, these networks are not appropriate for passing broadband digital signals. Wire parasitics are dominated by the approximately 1 nH/mm wire inductance which results in a 5 /mm reactive impedance at 1 GHz that scales linearly with increasing frequency. Tkachenko analyzed the reduction in inductance that results from reducing the area of the wire-bond loop ([ ] Figure 1) and found that the inductance varied as L(nH) = -0.15 + 0.46b + 0.69a  with a and b in mm. While simplified, the model shows that reducing the area under the loop results in lower inductance. Unfortunately, even the best ball-stitch wire bonds protrude approximately 50 m above the level of the die (Figure 2.) Collapsing the loop and controlling the conductor geometry opens the possibility of creating structures with small spacings between the conductor and the ground plane and even matched microstrip lines. Figure 1: Wire-bond loop geometry analyzed by Tkachenko. Figure 2: Conceptual cross-section of an optimized ball-stich wire bond connection (Amkor.) Aerosol Jet® Process In the Aerosol Jet® process, an ink is atomized to a fine mist and aerodynamically focused onto a substrate (Figures 3, 4.) Nanoparticle or micro-flake metal inks are normally used to print conductors. These inks can be oven-sintered at 120-200 C, or laser or flash sintered with the substrate remaining near ambient temperature. Currently, silver conductive inks dominate additive manufacturing, but copper nanoparticle inks are making rapid progress and should be fully qualified in the near future. A range of dielectric chemistries are available including epoxies, acrylates, urethanes, silicones, thermoplastics, and polyimides, many of which can be UV-cured in-situ to form 3D structures. The final focusing of the aerosol occurs in the tip which stands off from the substrate by 1-3 mm when printing fine features (10 m and larger.) Automation is available from XY for the printing of planar parts to 5-axis for printing fully 3D parts. Figure 3: Aerosol Jet conceptual schematic. Figure 4: Mist emerging from tip impacting substrate Printed Interconnects The concept of a printed interconnect from the package substrate to the die is shown in Figure 5. While greatly reducing inductance, the printed line does increase the shunt capacitance of the interconnect. If printed over a ground plane with a 5 m thick Parylene (≈3) dielectric, a 35 m wide trace would have a capacitance of about 5 pF/mm2 or about 0.14 pF/mm – about twice the capacitance of a bond wire. The area under the printed trace’s “loop” is negligible and it can be modeled and optimized as a microstrip line. A 35 m wide printed trace on 15 m of Parylene would have an impedance of 50 Ohms. The trace width could also be adjusted to provide a 50 Ohm impedance on a package substrate with a buried ground plane. If desired, the conductivity of the metal can be tailored to provide a significant real component of resistance. Silver conductors printed from the substrate to a four-die stack are shown in Figure 6. Figure 5: Conceptual drawing of printed interconnect. Figure 6: Printed conductive trace connecting four stacked die. Reducing the on-chip contact capacitance is an on-going effort. Printed interconnects have low contact resistance/unit area and can be significantly smaller than the >2x ball diameter of wire bonds (Figure 7.) While the printed trace may be wider than the contact, the capacitance of the trace outside the contact can be suppressed by the microns-thick dielectric coating used to isolate the sidewalls. Figure 8 shows contacts bussed together to form a low-impedance path to the power supply rails to suppress switching transients. Die-to-Die Inter-die connections are a second area where printed conductors could reduce the impedance discontinuities related to wire bonded connections. Nicholson and Lee demonstrated reducing reflections with a low-pass filter formed on a 127 m thick alumina substrate by widening the end of the microstrip line to locally increase capacitance ([ ] Figure 9.) A fully-matched structure could be formed by printing fill material in the gap with a dielectric constant modified to match the alumina substrate followed by printing a metal microstrip line across the fill material. Alternatively, the line width could be varied over the fill to provide an impedance match with the dielectric constant of the unmodified fill material. In-situ monitoring of the fill level during printing could compensate for Figure 7: Contact with reduced area to reduce contact capacitance. Figure 8: Bussed contacts with low inductance to suppress ground bounce. placement tolerances of the two die. Singh and Nirmal have shown that the image currents induced in a conductive bar in the gap could reduce the inductance of the structure by 50% ([ ], Figure 10). This could be accomplished by printing a dielectric fill in the trench and over coating the fill with a conductive coating. Alternatively, a full microstrip structure (ground plane, dielectric, and conductor) that is essentially electrically invisible could be printed across the gap between the die. Figure 9: Geometries for forming a LPF. Figure 10: Metallic bar inserted into the gap between ICs. Conclusions Printed conductors and dielectrics have the potential to significantly reduce impedance discontinuity issues in intra-package connections. Full 3D modeling of printable structures is needed to determine most effective, and cost-effective way to form RF interconnections in the Gigahertz regime.|
|Kurt Christenson, Senior Scientist
St. Paul, MN