Here is the abstract you requested from the dpc_2018 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Rapid Physical Prototyping of Microelectronic Systems using Heterogeneous Technologies with Silicon Interposers|
|Keywords: silicon, interposer, 3D|
|The market for Semiconductor Intellectual Property is well served for standard process technologies but not all functions are offered in all processes. Mixing and matching high performance digital CMOS, analog components, MEMS and optical devices can be an expensive and risky endeavour. Users often want to create a functional prototype for testing and sampling before committing to full production tooling or custom process development. Silicon Interposers can fill the gap by allowing users to mix and match components in different fabrication technologies with numerous advantages over Printed Circuit Board implementations. Silicon Interposers are substrates with signal pass-throughs made possible by Through-Silicon-Vias (TSVs). Metallization on either side of the interposer can be used to provide interconnect between mounted components, including passives, but the bottom side interconnect can also be used as Under-Ball-Metallization (UBM) to transform the interposer into a surface-mountable module in a larger system. The TSV connections from top to bottom of the interposer make it a versatile and efficient packaging system. Silicon interposers have a variety of advantages over printed Circuit Board (PCB) implementations including improved size, speed, power, excellent rigidity, good thermal matching to silicon components, minimal outgassing or contamination in extreme environments, well-controlled RF performance, and excellent reliability. Innotime has designed a simple, regular base array of TSVs with common spacing and size. The base arrays are purchased from multiple sources and are inventoried to reduce customization cycle time. Base array wafers are held in inventory prior to patterning of the top side and bottom side metallization so that prototypes can be completed rapidly in a few mask steps. This approach reduces cycle time for new designs and offers a range of wafer size and TSV performance at reasonable cost.|
|Gord Harling, CEO