Honeywell

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Memory Packaging Trends: From wire-bond to TSV!
Keywords: Memory Packaging, Flip-chip, TSV
There are many different memory device packaging options, implying a wide range of packaging technologies ranging from low pin-count SOP packages to high pin-count TSV options, all depending on product requirements like density, performance, and cost. In 2016, wire- bond BGA accounted for more than 80% of the packaging market in dollar terms. Also in 2016, flip-chip began making inroads in DRAM memory packaging and is expected to grow at a ~20% CAGR over the next five years, accounting for >10% of the total memory packaging market. Increased adoption in the DRAM PC/server segment, fueled by high bandwidth requirements, drives flip-chip growth. Spurred on by high bandwidth and memory chips’ low latency demands for high-performance computing in various applications, TSV is being employed in high-bandwidth memory devices. The 2016 TSV market was only <1% of the total memory market, but this will grow to a >30% CAGR, reaching ~8% of memory packaging in dollar terms by 2022. NAND flash devices’ main requirement is high storage density at low cost. NAND chips are stacked using wire bonding in order to provide high density in a single package. NAND flash packaging will remain in wire bond BGA form and will not migrate to flip-chip. However, TSV stacked NAND will be adopted by some players to increase data transfer rate for high- end applications. The presentation will focus on the evolution and market and technology trends of different memory packaging platforms.
Santosh Kumar,
Yole Developpement
Lyon , Lyon
France


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