Here is the abstract you requested from the dpc_2018 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Stretching Time in FPGAs: Chaos Enhanced Entropy using Asynchronous Logic|
|Keywords: FPGA, Random Number Generation, Oscillator|
|We report on a new time-stretching method in Field-Programmable-Gate-Arrays (FPGAs) that exploits the combination of asynchronous logic and dynamical systems in order to realize novel entropy sources. FPGAs are a flexible platform for implementing logic-based functions on a large scale. Such systems have become increasingly used throughout engineering applications for data processing and collection. Typically, FPGAs are operated in a mode where a periodic clock updates a finite-state machine that acts as a small computer, where all of the computer operations are updated synchronously. However, FPGAs can also be used in an unclocked or asynchronous mode-of-operation, where the ‘on’ or ‘off’ signals of the logic gates propagate throughout the FPGA in continuous-time. Recently, this asynchronous mode has allowed for new studies into dynamical systems and network science; both genetic and neural networks found in nature operate by propagating ‘on’ or ‘off’ signals throughout a system of links and nodes, where the propagation times of those signals can play a fundamental role in the dynamics of the systems. Similarly, in asynchronous FPGAs, the propagation times of signals depend on their paths through the gate arrays. Thus, FPGAs have recently become a platform for studying dynamical phenomena and applications of these studies have begun to emerge. For example, it was recently demonstrated that an unclocked FPGA network can be used a reservoir computer, a framework for interpreting complex data. Chaos in asynchronous FPGAs has also recently been demonstrated as a new source for high-speed random number generation. The re-programmability and prevalence of FPGAs throughout the electronics community opens up possibilities for large-impact changes to be implemented using simple software updates. Our goal is to develop dynamically enhanced applications for such purposes. Time-stretching in FPGAs using our methodology utilizes a logic structure that stretches or squeezes the width of a logic signal or pulse in real time. Under a typical clocked mode-of-operation, a logic signal’s time interval or pulse width can be measured in terms of the FPGA update speed, and that information can be stored using a counter. Thus, a higher clock-speed typically provides better resolution for pulse-width measurements and modifications. In order for a clocked system to then stretch or squeeze the pulse width, processing must take place in order to compute and then output the newly desired pulse width, which will also be discretized in time. We remove the limitations of the clock speed and processing time by designing a framework for a network of logic gates which can implement an arbitrary time-stretching function without being discretized in time. We then use this FPGA time-stretching modality in order to realize a variety of simple, continuous-time chaotic systems with positive entropy. Overall, time-stretching within asynchronous FPGAs is a new building block for developing dynamically enhanced FPGA-based technologies. Future applications range from wide-band tunable pulse-generators to new and flexible entropy sources in FPGAs for random number generation.|
|Seth D. Cohen, Research Physicist