Here is the abstract you requested from the dpc_2018 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Successful FPGA Obsolescence Form, Fit, and Function Solution Using a MCM and DER™ to Implement Original Logic Design|
|Keywords: FPGA to Discrete MCM Conversion, IC Obsolescence Solutions, Inter-Cavity Substrate Design|
|In some configurable Field Programmable Gate Array (FPGA) obsolescence situations, a hybrid or Multi-Chip Module (MCM) solution can produce a form, fit, and functional (FFF) replacement product with the aid of Die Extraction and Re-packaging (DERTM) to obtain the discrete component building blocks required within the FPGA schematic design. For the case study proposed in this abstract, an obsolete 64-pin Applied Micro Circuits Corporation (now Macom) bipolar FPGA with an 1800 gate capacity was previously used to implement the logic functions of six discrete integrated circuits (three 54S181’s, one 54S182, one 54S151, and one 54S374), three NAND gates, two AND gates, and one pull-up resistor. Due to the high-voltage supply and signal requirements (5.5V) within the original system, there are no candidate non- volatile programmable FPGA donor parts still available which can implement the desired circuit for a drop-in replacement. Although there is no surviving firmware from which to derive the original source code for recompilation of the known logic (see Figures 1 & 2), the FPGA can be implemented from the original DoD drawings (see Figure 3 for pin listing). With DERTM, all required devices can be resolved in die form, in any required volume, and mounted on an internal cavity interposer within the package cavity to recreate the original programmed FPGA in the required footprint. Subsequent production testing of the test vector set called out within the test document can be implemented over the full -55°C to +125°C military temperature range to provide a proven successful form, fit, and functional (FFF) replacement product in the identical package footprint. The packaging challenges involve an inter-cavity substrate multi-chip translator that routes the individual chip connections to a perimeter bonding system consistent with the original device signals and either a specialized low-temperature curing epoxy fill to encase the module or a localized high-temperature seam sealing capability to affix a metal lid. The associated paper/presentation will cover photos of the raw components before and after die extraction, the design requirements for the inter-cavity substrate, the die mounted and bonded out on the substrate (MCM), and the final device appearance. Electrical parametric and functional test results will be reported relative to the original component requirements. Overall cost savings to the DoD for this design is on the order of $1.5M due to redesign avoidance. Figure 1: Part 1 of Overall Design Schematic. Figure 2: Part 2 of Overall Design Schematic. Figure 3: I/O Signal Convention to be Implemented.|
|Erick Spory, President and CTO
Global Circuit Innovations, Inc.
Colorado Springs , Colorado