Here is the abstract you requested from the dpc_2018 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Innovative Wafer Fan-out Technologies -- Heterogeneous Integration for a Connected World|
|Keywords: Fan out, heterogeneous integration, system in package|
|Innovative Wafer Fan-out Technologies - Heterogeneous Integration for a Connected World Advanced packaging technologies have increased in complexity over the years, transitioning from single to multi-die packaging, enabled by 3- dimensional (3D) integration, System in Package (SiP), Wafer Level Packaging (WLP), and increasingly creative approaches to embedding die. These new innovative packaging technologies enable more functionality and offer higher levels of integration within the same package footprint and often in an intensely reduced footprint. In fact, the latest advancements in heterogeneous integrated semiconductor packaging are able to provide reduced form-factor, increased data transfer rate and improved signal integrity and memory bandwidth, all with reduced power and improved thermal performance. In today's connected world with the proliferation of connected devices forcing continually higher system- level performance, semiconductor packaging has stepped up to play a pivotal role in providing the solutions to the newest system-level requirements. To further compound the semiconductor packaging challenge, the continued scaling of transistor geometries for semiconductor devices further increases the demand on the next-level interconnect technologies. Heterogeneous integration of memory, logic, and power management devices is increasingly becoming the norm for next-generation mobile, high- performance graphics, and network applications. This requires advanced packaging technologies with capabilities for very high signal routing densities, efficient power distribution, and superior signal integrity. In addition, 3D package integration is often required, especially for mobile applications. This places an increased emphasis on the package technology's z-height reduction and thermal performance capabilities. Traditional organic laminate substrates that utilize flip chip bonding have met the semiconductor industry's advanced interconnection needs for over 15 years. With the continued advancements in materials and processes, laminate substrates are expected to satisfy the majority of advanced package performance and cost requirements for years to come. However, the feature size limitations and the electrical and thermal performance constraints will continue to restrict laminate substrates from meeting the integration requirements for next generation mobile and networking applications. Emerging silicon-based interconnection technologies, such as through silicon via (TSV) have shown promise in this area. By leveraging the back end of line (BEOL) damascene processes of the wafer fab, multi-layer sub-micron signal trace densities can be achieved. However, the supply chain limitations and intrinsic cost implications have limited the proliferation of 3D IC technology. In particular, for silicon interposers, there can be an undesirable effect to z-height and electrical performance due to the inherent thickness and parasitics of the silicon interposer. This paper will discuss innovative wafer fan-out technologies that meet the heterogeneous integration requirements for an increasingly connected world, bridging the gap between organic laminate-based substrates and inorganic foundry-based silicon interconnect solutions.|
|Curtis Zwenger, VP, Advanced Package & Technology Integration