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Panel chip last fan-out warpage analysis and control strategy
Keywords: panel fan-out, chip last fan-out, warpage control
Fan-Out technology is the most popular advanced assembly process. The most mature one is wafer form chip first process. It’s widely used for high end products. For the high performance application, large die size and chips integration is the trend. It makes that die configuration resulted wafer corner area waste and fan-out process yield loss resulted good die consumption becomes a huge burden. Panel level chip last fan-out is the best solution for cost reduction. A two chips, 2um line width / 2 um space and 4 copper layers fan-out device is chosen to be the test vehicle for panel level chip last fan-out process evaluation. However, its process control is much difficult than wafer level chip first fan-out; especially, by process panel level warpage control. Thermal stress simulation by finite element method is a powerful scheme for warpage evaluation. A tool with deep focus of length to measure thermal dynamic panel warpage is crucial for providing sufficient data for modeling validation. An equipment based on three dimensional digital image correlation method is used to measure the temperature elevated panel level warpage at several interval statements during the process. According to the well correlated model, the impact of materials properties and thickness including glass carrier, underfill, epoxy molding compound and several parameters is evaluated. With proper materials and dimensions selection, the fan-out package is successfully assembled by cost efficient panel level chip last process. Meanwhile, the selected combination has good package warpage, too. The design guideline comes from this specific test vehicle is general, but not universal. The package area to die area ratio (or said fan-out ratio) for kinds of fan-out packages has large difference. The parameters analysis for packages has fan-out ratio from 1.05 to 3 and copper layers from 2 to 4 is executed in this paper to provide a universal design guideline for panel level chip last fan-out packages.
Ian Hu, Principal Engineer
Advanced Semiconductor Engineering, Inc.
Kaohsiung, Taiwan
R.O.C.(Taiwan)


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