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Wafer Nano Topography and Edge Roll-Off Metrology for 3D Monolithic Integration
Keywords: 3d Monolithic integration, wafer nano topography, edge roll-off metrology
Today complexity and cost of semiconductor manufacturing at leading edge (<10 nm) has increases the interest for 3D approaches. Among the 3D integrated circuits’ scheme, 3D VLSI Leti CoolCube TM approach aims to stack transistor layers. Nevertheless its implementation require high quality top layers and low temperature process at wafer level. In order to achieve this, low temperature molecular bonding have been chosen. To achieve this challenging bonding, an extreme good level of flatness has to be achieved on the bottom structured layers. Thus Chemical Mechanical Planarization (CMP) is crucial. Consequently the CMP process need to be controlled very tightly. The present paper focus on the demonstration of Phase Shifting interferometry (PSI) as a solution to measure the topography of the wafer at both die level and at the extreme wafer edge level with high lateral resolution and from several hundred of nm to few nm level of amplitude. In a first step, PSI technology is explained and metrological validation from the point of view of accuracy and repeatability and reproducibility is demonstrated. In a second step, the methodology to achieve both die level and extreme edge measurements is explained. Finally two examples of these measurements in 3D monolithic CoolCubeTM wafers are shown. Results and performances are presented and compared to other techniques. Actual performances are quantified and remaining challenges and possible solutions are discussed.
M. Abdel Sater,
CEA LETI
Grenoble, Cedex
France


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