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Multi-die Connectivity and the Proposition forHeterogeneous IC Packaging
Keywords: Multi-die Connectivity, Heterogeneous IC Packaging, High Bandwidth Memory
Recently, heterogeneous integrated circuit (IC) packaging trends have been addressing the need to handle ever increasing logic die sizes, more in-package memory, such as High Bandwidth Memory 2 (HBM2) and higher power. Looking forward, these trends are extending even further. Package sizes in excess of 100 x 100 mm are on the drawing boards. Application specific integrated circuit (ASIC) sizes continue to grow pushing full reticle sizes, even into 7-nm processes. Memory package counts are increasing, and new combinations of logic-logic and logic-memory types are being seriously considered. Now, the ultimate goal for heterogeneous packaging, to truly be able to embed system on chip (SoC) functional blocks at the package level, is being reexamined in the context of advanced packaging progress. SoC designs require that functional blocks be redesigned for every silicon node, a very demanding and time-intensive technical challenge, especially for the high-speed input/output (I/O) blocks. High-speed block electrical validations in silicon test chips add significantly to the time to market for a custom IC, and often form the critical path for a complex IC tape-out. Keeping these electrically sensitive designs in a proven, older and economical silicon node is a powerful motivation to recombine some of the key SoC building blocks at the package level, reducing the total cost and time to market for a system-level design. Enabling this level of IC package integration requires the IC package to provide very-high density die-to-die routing capability, excellent electrical signaling capability and power delivery, assembly process stability including warpage control, final package coplanarity control, adequate thermal dissipation and size scalability from 35 x 35 mm to 100 x 100 mm sizes. To address this opportunity, Amkor has developed several key technology modules. The 2.5D Through Silicon Via (TSV) package construction is now mature and already in high-volume manufacturing, and forms the baseline to compare other heterogeneous package constructions. Design rules have been derived that permit a very predictable package electrical performance, package mechanical reliability, package testability and thermal performance. This predictability is at the very heart of any successful heterogeneous package. By way of example, the IC fab processes are a model of predictability. Functional blocks are integrated in a feature-rich simulation environment to produce first-time right extremely complex, multifaceted designs. Enabling this success are detailed models of transistor and signaling behavior so detailed, that designs are created in abstraction with the extremely complex logical Boolean functionality at the core of the design process. The detailed physical to electrical models are verified by test vehicles in the IC fab, and integrated into the final design environment by the electronic design automation (EDA) tool suppliers. Advanced IC package development at Amkor also takes a vehicle demonstration approach. The development and validation of die to die connectivity in the package environment is at the very core of the successful heterogeneous integration. From the heterogenous package design standpoint, there are two items that must be known with certainty: (1) the mechanical routing of signals and power, and (2) the 3D construction of that interconnect such that the electrical performance can also be predicted with certainty. There are many approaches which have been developed or are being developed in the industry to provide predictable performance. The list of metrics that permit a comparison of the relative merits of these approaches includes signal routing line/space, layer counts, dielectric thicknesses, copper surface roughness, extensibility to larger x-y sizes and others. This comparison deserves serious consideration. Larger x-y package sizes have pushed Amkor to consider more tunable physical characteristics, such as effective coefficient of thermal expansion (CTE), so that larger sizes can be accommodated without incurring excessive stress levels due to CTE mismatches. Much of this work has been made possible with the implementation of a new class of moldable dielectric materials, advances in copper (Cu) pillar plating technology, and fine-line multilayer redistribution layer (RDL) championed in the SWIFT(R) packaging development. As a part of the tool set combined SWIFT, S-Connect(TM) permits the combination of very fine line (1 um line and space) geometries made possible by dual damascene, with the versatility and mechanical tunability of SWIFT design.
Mike Kelly, VP, Adv Package & Technology Integration
Amkor Technology, Inc.
Tempe, AZ

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