Here is the abstract you requested from the dpc_2018 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Achieving Monolithic SoC Performance with a Lower Cost, Rapidly Upgradeable 2.5D Modular Architecture: Challenges and Opportunities|
|Keywords: Monolithic SoC, 2.5D, Modular Architecture|
|The cost of application-specific advanced node SoCs (e.g. 14nm CMOS) can be prohibitive for many DoD applications, due to relatively low production volumes compared to commercial products. In addition, the SoC design cycle time may be inadequate to respond to emerging threats, which leverage rapidly evolving commercial technology. Disaggregation of SoCs into modular 2.5D architectures provides a potential means to reduce the non-recurring engineering cost and improve the turnaround time of advanced node microelectronic systems by reusing high value IP that has been pre-fabricated as chiplets for broad commercial consumption. This presentation will discuss the technical challenges of disaggregation, which includes maintaining power efficiency and compact size followed by an analysis of the relative cost and time improvement that can be achieved with a modular architecture for an exemplary system.|
|Pavel Borodulin, Fellow Engineer