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Yearlong 500 C Operational Demonstration of Upscaled 4H-SiC JFET Integrated Circuits
Keywords: SiC, Integrated Circuit, Fabrication
This work describes recent progress in the design, processing, and testing of significantly upscaled 500 C durable two-level interconnect 4H-SiC JFET IC technology undergoing development at NASA Glenn Research Center. For the first time, stable electrical operation of semiconductor ICs for 1 year (8760 hours) at 500 C in air atmosphere is reported. These groundbreaking durability results were attained on two-level interconnect JFET demonstration ICs with 175 or more transistors on each chip. This corresponds to a more than 7-fold increase in 500 C-durable circuit complexity from the 24 transistor ring oscillator ICs reported at HiTEC 2016 [1]. The prototype ICs tested for over a year at 500 C include a 195-transistor 16-bit random access memory (RAM) chip and a 175-transistor clock signal generator with electronically selectable divide by 2 or 4 output signal (2/4 Clock) achieved using a 21-stage ring oscillator base clock driving D-type flip flops. Both chip designs demonstrated desired functionality at 25 C and 500 C without any change to input signal or power supply voltages and only inconsequential changes to output signal voltages despite the 475 C disparity in operating temperature. Following the first 100 hours of 500 C burn-in, functional chip output signal properties (e.g., logic voltage levels and clock frequencies) have changed less than 10% over the remaining thousands of hours of 500 C operational testing.
Philip G. Neudeck, Electronics Engineer
NASA Glenn Research Center
Cleveland, OH
USA


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