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Digital Logic Synthesis for 470 Celsius Silicon Carbide Electronics
Keywords: Silicon Carbide, Design Flow, Extreme environment, high temperature
Advancements in Silicon Carbide (SiC) digital integrated circuit (IC) design [1] have enabled the ability to design complex, dense, digital blocks [2]. Because of the large number of transistors, these complex digital designs make the time and risk of hand-crafted digital design, which has been the norm for SiC designs, too costly and risky. The aid of an automatic synthesis place and route digital flow is necessary for timely and accurate dense digital designs. An automated digital flow in SiC digital design presents new challenges, such as building a new tool chain for extreme environment timing extraction as well as the complexity of synthesis, placement, timing enclosure, and routing over a > 400C operating range [3]. Proposed is a solution to a full digital flow with a focus on high temperature SiC digital synthesis. This digital flow is fully integrated with the characterization of a standard cell library that considers the variation of voltage, temperature, and process characteristics. The automatic characterization process generates performance and timing models over a very wide temperature range. These timing models are utilized in a top-down approach to verify the design. A digital (Verilog) simulator is used to verify the Register Transfer Logic (RTL) from behavioral to high temperature gate- level using min, nom, max delay timing of the standard cell library. Liberty files for static timing analysis (STA) are generated from the characterization process as well. SPICE simulations at high temperature are run in conjunction with custom scripts to extract setup and hold tables, as well as other standard liberty information. The verified RTL is synthesized, placed, and routed using the open source tool, Qflow [4]. The synthesis process can focus on a specific temperature, voltage, and process liberty file to create a technology and operation corner specific netlist. Qflow place and route uses technology-specific physical layers, exported from the layout, to create a final physical design. The final physical design is then integrated with custom analog/mixed signal blocks as an integrated layout view. The gate-level Verilog netlist is also imported for schematic vs layout checking, and the design function is validated via netlisting to Verilog event-driven simulation. Physical verification is completed with simulation of parasitically-extracted design. The final imported verified design is then integrated into the top-level ASIC. A digital controller for a 10,000- pixel UV focal plan array in a SiC CMOS process was designed using this high temperature digital flow. The controller is comprised of a state machine and several counters and shift registers that are programmable by the user depending on field use. The top- level digital design generates anywhere between 900 and 1000 gates depending on the temperature corner with a total footprint of 14mm2. Typical SiC processes present a non- monotonic clock speed over temperature. The advantage of this integrated flow allows the designer to target a temperature corner for the netlist design but verify its operation over a > 400C operating range. This behavior was observed from STA for the digital controller clock. Standard cells used for this design were also used to create ring oscillators in the same run. Hardware data from these ring oscillators can be fed back into the timing extraction models to predict the operation speed of the digital controller before full hardware test. This flow is being implemented, in earlier stages, for use with NASAs SiC JFET-R process [5] to create a high temperature communication protocol interface. Comparative examples of synthesis in multiple SiC technologies will be presented.
Nick Chiolino, Design Engineer
Ozark Integrated Circuits, Inc.
Fayetteville, Arkansas
United States


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