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High Temperature SRAM in SiC CMOS
Keywords: Silicon Carbide, High Temperature, Memory
As high temperature electronics increase in complexity, data storage requirements will continue to increase. Upcoming high-temperature CMOS silicon carbide (SiC) circuits demand high-density memory that is compatible with existing digital logic. Microcontrollers and data handlers require the accessibility provided by standard memory array techniques in high density. Previous work with high-temperature SiC memories include flip-flop based designs[1] as well as a 4x4 array with JFETs[2]. An array of flip-flops fabricated in the same manufacturing run resulted in a specialized data array with a density of 49.7 bits/mm^2. However, such an array suitable for a SiC microcontroller would consume the majority of the available die area. High temperature, high density memory is an enabling technology for increasingly complex computations and processing in extreme environments. This paper presents the first SiC CMOS SRAM, as well as the densest and largest SRAM array in SiC to date. The HiTSiC® CMOS process was used to implement the memory array. The process has a minimum channel length of 1.2 um, with one layer of high temperature metal. Nominal power supply voltages range from 12V to 15V, depending on application. Simulation models based on measured data and process variations were used to validate the robustness of the design. A library for high temperature SiC CMOS SRAM development was designed. An SRAM bit-cell was designed and simulated for 2 MHz operation over a temperature range of 25℃ to 470℃. A standard 6-T CMOS topology[3] was employed to allow for low DC current consumption. The final bit-cell dimension was 37.2 um x 42.3 um. Read and write phases were driven based on a symmetric external clock, limiting the impact of timing fluctuations over temperature, voltage, and process variations. Row and column access circuits were sized for an 64x128, 8 kbit array. Due to the considerable limitation of only one metal layer, the polysilicon layer was used for supplemental power and ground connections, as well as word line routing. With the word lines routed horizontally, the array was made tall and narrow to minimize the length of critical polysilicon routes. The positive and negative supplies, as well as the bit lines, were prioritized to run on metal throughout the entire design. The final 64x128 bit array dimension was 2945 x 6080, yielding a density of 457.5 bits/mm^2. Compared to the specialized data array mentioned earlier, the SRAM design enables random access while increasing the layout density per bit by a factor of 9. The memory array was fabricated as a test structure in a larger system. Due to area restrictions in the layout, the test array was limited to 8x96, and the address and data inputs were routed through a shift register to reduce the input pin count. Output timing and clock operation remain unaffected by the design, allowing for a larger array to be implemented. The final paper will present measured data from the SRAM array over temperature. Input and output timing, as well as validation of memory retention will be demonstrated. Full array performance will be estimated.
Matthew Barlow, Senior Engineer
Ozark Integrated Circuits, Inc
Fayetteville, AR

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