Here is the abstract you requested from the hitec_2018 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Co-optimized Reliability and Parasitic inductance in Small Footprint Lateral Silicon Carbide MOSFET|
|Keywords: SiC MOSFET packaging, thermal cycling reliability, parasitic inductance|
|Increasing power density in power electronics is driving a need for improved packaging methods for co- optimized high frequency performance, thermal dissipation and reliable operation, especially at high temperatures. Silicon Carbide (SiC) devices offer great opportunity as wide bandgap semiconductor devices, which maintain stability over wide temperature ranges, especially when compared to Silicon (Si) based devices. A novel flip-chip packaging technique for SiC power devices was developed at the University of Arkansas . This new package reorients a bare die from a vertical device to a lateral device by utilizing a copper connector that routes the drain connection to the top side of the die. This study involves an investigation of achieving a co- optimized packaging configuration for thermomechanical reliability and low parasitic inductance. By orienting this SiC switch laterally, the unique 3D drain connector dramatically reduces the ringing at aggressive switching speeds used in power electronics when compared to Commercial Off The Shelf (COTS) devices. However, the design of this drain connector holds importance for high temperature operation, interconnect reliability as well as manufacturability. Effects of the packaging design, including materials, layout and and solder pitch size were investigated from a thermal cycling reliability aspect. Electrical performance, such as parasitic inductances of the device, was also investigated using finite element analysis (FEA) simulation. Several drain connector architectures were evaluated for their fatigue life capability of solder interconnects under thermal cycling (according to Darveaux�s model ) in conjunction with the parasitic inductance using FEA simulation. Based on the simulation results, an optimized architecture was selected and fabricated for prototype demonstration, and the electrical performance compared with state of the art devices demonstrated clear improvement. In addition to the design optimization study, this talk will address the device manufacturability concerning the 3D stacking, including process and material optimization considerations for flip chip processing for high temperature SiC electronics and integration with gate driver devices. The complexities associated with heterogeneous integration of these devices also illustrates the need for alternative reliability test methods, particularly when considering high temperature operation outside of normal JEDEC or AEC reliability test protocols. These challenges will be discussed along with learnings from alternative reliability demonstrations for high temperature interconnect testing.|
University of Arkansas