Honeywell

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Bumping process effect on CPI reliability
Keywords: CPI, Bumping, Reliability
Abstract Flip chip technology is widely used in advanced integrated circuit (IC) package. Chip package interaction (CPI) be¬came critical in flip chip technology that needed to be addressed to avoid electrical or mechanical failure in products. When addressing CPI challenges, different areas have to be considered, ranging from silicon BEOL design and processing, bumping design and process, package assembly process, assembly bill of material (BOM), and substrate technology. Controlled collapse chip connection (C4) bump technology provided the inter-connection between the IC to package substrate for high-performance, leading-edge microprocessors. It is very critical for chip package interaction (CPI). With the transfer to lead free technology, bumping process plays more and more important rule for chip package interaction reliability. In this paper, we focused on bumping process effect on the CPI reliability. The bumping process has been reviewed and CPI reliability issues induced by the bumping process like particles, incomplete Ti deposition, UBM voids, missing Ni on UBM, UBM undercut, Cu pad oxidation and contamination, photoresist opening damage have been discussed. Bumping process optimization have been taken to reduce those defects and improve CPI reliability.
Lei Fu, Principal Member of Technical Staff
AMD
Austin, TX
USA


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