Here is the abstract you requested from the imaps_2018 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Large Size FCBGA Stress and Thermal Challenges and Characterization|
|Keywords: HFC-BGA, Large size package, Warpage|
|Recently, high speed communication packages require much larger chip sizes and the increased ball/lead counts, in order to meet high input/output (I/O) functionality, requires large size substrate (>50x50 mm2) to content it. High performance flip chip ball grid array (HFCBGA) package is the most popular package type for the high end communication market, which has a metal lid, as heat spreader, on the top of the chip and substrate for warpage control and chip protection. With high quality thermal interface material (TIM) between the chip and lid, the thermal dissipation capability is outstanding (>100W), too. However, the good thermal, stress and warpage result comes from professional design and high quality manufacture capabilities. For high thermal performance requirement, the TIM should have high thermal conductivity, thin bond line thickness (BLT), good coverage rate and no delamination, which needs no degradation after reliability test. How do these factors impact on junction to case thermal resistance, the widely used index for high power package thermal performance definition, are evaluated in this paper by computational fluid dynamics modeling simulation. Generally, the delamination trends to appear at the interface of TIM and chip. Finite element method is conducted to evaluate not only the package warpage, but also the TIM/chip interface stress. To control the warpage within criteria and minimize the TIM/chip interface stress to avoid any delamination occur for large size HFCBGA is really a big challenge. As the package size and die size increase, the die to package interaction failure risk increases significantly due to a larger coefficient of thermal expansion (CTE) mismatch region between die and substrate. Meanwhile, design for warpage control and TIM/chip interface stress reduction are conflicting in general. This paper evaluates key factors for mitigating warpage and improved thermal dissipation capability by eliminating TIM/chip interface stress, including the lid dimension, BLT thickness and TIM material. Ring type design is the other choice for large size HFCBGA. It has the benefit of better thermal performance due to exposed die design, but less warpage control ability and loses die protection capability. Each of lid and ring has its own advantages, which one is better based on demand of die protection. A test vehicle with the size around 65x65mm2 was developed to validate the evaluation. With the proper selected structure and materials, the package can meet all the assembly criteria.|
Group R&D, Advanced Semiconductor Engineering, Inc.,