Device Packaging 2019

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Productivity Comparison of Wafer Transport Architectures in PVD Tools Used for Fan-Out Packaging RDL Barrier/Seed Formation
Keywords: Barrier/Seed Layer PVD, Equipment Productivity, Cost of Ownership
Physical Vapor Deposition (PVD) systems are widely used in the semiconductor fabrication industry, both for front-end applications in the wafer fab and for back-end applications at device packaging houses. The copper damascene process used to create the multi-level metal interconnects found in microprocessors and other logic-heavy integrated circuits is based on repeatedly forming barrier, liner, and seed layers from sputter deposited metals, for example Ti, TiN, and Cu, before a subsequent copper electroplating step creates the signal-carrying plated copper metallization lines. Similarly, in fan-in wafer level packaging, in fan-out wafer level packaging (FOWLP), and in fan-out panel level packaging (FOPLP), sputter deposited Ti and Cu are the base on which electroplated copper Redistribution Layers (RDLs) are built. In semiconductor front-end PVD, cluster tool wafer transport architectures (Fig. 1) have been widely used since the mid-1980s [1]. In these PVD cluster tools, wafers or substrates are handled many times as they make their way from the entrance loadlock to the exit. In fan-out packaging applications, for example, where reconstituted mold compound wafers will see a degas step, a pre-clean step, a Ti PVD step, and a Cu PVD step, the wafer will be touched by the central handling robot at least seven times, and the wafer will be touched by lift pins another six or more times as the wafers are raised or lowered in the various process modules. Each of these mechanical transfer operations has a fixed and dedicated time budget for the transfer, generally a function of the central robotic handler speed, and each of these mechanical transfer operations also has a “lost opportunity” budget, as a robot occupied with a transfer from the Ti PVD module to the Cu PVD module has no opportunity to be doing anything else but that specific transfer. As a result, optimizing the cluster tool scheduler software can become quite involved [3], [4]. Other wafer transport architectures are more efficient from a wafer handling perspective. In carrier-based PVD tools based on linear transport architectures (Fig. 2), wafers or substrates passing through are directly touched only a few times as the carrier-borne material makes its way from the entrance loadlock to the exit. As a result, the mechanical transfer time budget for a linear transport system is considerably less than for a cluster tool, as there is essentially no “lost opportunity” budget. One robotic wafer handler (Input) is only occupied loading wafers, from FOUP to carrier, just as the other handler (Output) is only occupied with unloading wafers from the tool. Transport time overhead per wafer on linear transport systems is quite low, and scheduler software optimization becomes less onerous too, as a result of the simpler wafer transport architecture of linear transport tools. We analyzed the relative throughput of cluster and linear transport PVD tools for a typical FOWLP barrier/seed layer (1000Å Ti / 2000Å Cu) sputter deposition, and present details in this paper of how the time spent moving wafers to various processing chambers affects overall system productivity. In the case of the cluster tool architecture, with its central wafer handling robot, wafer throughputs are approximately 50 wafers per hour, while on the linear transport system wafer throughputs as high as 240 wafers per hour are possible. We also present details on how the significant difference in system throughputs greatly affects the relative Cost of Ownership (COO) per wafer processed, with the linear transport system returning COO numbers half those of the cluster PVD tool.
Paul Werbaneth, Global Product Marketing Director
Intevac, Inc.
Santa Clara, CA

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