Here is the abstract you requested from the imaps_2018 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Packaging and Integration Strategy for mmWave Products|
|Keywords: mmWave, Packaging Strategy, Integration Strategy|
|This paper is a follow on to the paper presented at the IMAPS 14th International Conference DEVICE PACKAGING and will provide a more comprehensive case studies on a few different system integration. The packaging options vary widely based on the end market requirements, from performance, thermal, types and numbers of antenna arrays as well as the RF trasceiver ICs. Tied closely to these performance related requirements are sometimes competing trade-offs of reliability, form factor and cost. We will present assessment of packaging structures for (a) high performance mmWave network product and (b) consumer/mobile product. The former (a) is generally not challenged by form factor and can, in general, be enhanced by addition of more antenna arrays and RFICs. However, care has to be taken to address the thermal solutions for effective heat dissipation as well as manufacturability issues as the package size may target ~400mm2 for Gen 1 and double or triple the area for subsequent generations. For (b), the primary drivers are cost and form factor. Integrated with the added issue of managing antenna propagation and losses, generally require antenna in package (AIP) integration. The integration of the antenna within the same package as the RF SiP greatly reduces the difficulty at the system level. This approach coupled to aggressive miniaturization of the antenna itself, using the same substrate technologies as the SiP leads to a new class of sub-systems termed Antenna in Package (AiP). This is extremely challenging from a design, manufacturabilty and test perspective. For example, Fan out wafer level packaging, such as eWLB packaging provides extremely smooth copper surfaces with tigh etch tolerance compared to standard laminate based packaging. However, having mulitport antenna structures fabricated in fan out technology with inductance matching and efficient ground ports, continue to be problematic. Hence adoption of 3D structures, in conjunction with SIP integration (with inductors and IPDs) can potentially provide relief. Inductors can also be built into the eWLB structure using the RDL as well as in the laminate packages using substrate embedded thin film cores. Co-design of the antenna, matching circuitry and the RF/baseband circuits is critical to meeting the performance goals. Typically, the design methodology uses a combination of circuit and electromagnetic simulation tools to create a design progressively from basic schematic representation to a complete 3D electromagnetic representation of the layout. The key design constraints when designing an integrated antenna for an AiP module consist of: ‐ Miniaturization of the antenna to fit into a small footprint. Typically the antenna footprint target is a reduction of a factor of 2 to 3 compared to a discrete antenna. ‐ Adaptability of the antenna topology to be realized using the chosen SiP technology (organic, or fan out package substrate or mix with IPD) ‐ Return loss over the operating bandwidth. This can be relative to 50 ohm or some other impedance chosen relative to the RF transceiver impedance ‐ Radiation efficiency to ensure minimum loss within the antenna structure ‐ Radiation pattern to match system and regulatory requirements ‐ Sufficient margin in terms of operating band to allow for the effects of ground plane size on antenna frequency tuning. Typically this needs to be at least 5% more than the operating band for 2.4 GHz ISM band antennas. Substrate manufacturability issues such as effect of copper roughness on insertion loss and low Dk, Low Df dielectric materials will be key contributors for meeting the overall performance requirements. Assembly, manufacturability and test (probe, ATE, bench, system) will also be covered in this paper.|
STATS ChipPAC Inc