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|Chip Package Interaction: Understanding of Contributing Factors in Back End of Line (BEOL) Silicon / Cu Pillar Design and Applied Process Improvements|
|Keywords: Chip-Package Interaction (CPI), BEOL/Cu Pillar Design, BEOL/Cu Pillar Process|
|ABSTRACT The initiation of cracks in the brittle ultra low-k dielectric material in the Back End of Line (BEoL) on advanced node silicon devices is of major concern for assembly processes. It is attributed mainly to various combinations of the Chip-Package-Interaction (CPI) effects. This challenge is further amplified by the adoption of Cu pillars to replace conventional solder bump flip chip interconnects as the device bump pitch shrinks and the demand for higher I/O counts per area soars. The high modulus Cu pillar transfers more thermo-mechanical stress to the ultra low k layer and increases the risk of dielectric cracks. The adoption of Cu pillars as interconnects is inevitable because Cu pillars offer superior electrical performance and a better capability of forming finer pitch joints than the solder bump reflow process. It is therefore important to understand the CPI challenges of Cu pillars on ultra low k chips and more importantly to find knobs to risk mitigate packaged induced failure modes in the BEoL. This paper describes major contributing factors to the CPI risk and reveals the mitigation strategy successfully applied by GLOBALFOUNDRIES. The paper focuses on design-related factors in the BEoL that contribute to the risk for CPI related failures, like local metal density changes underneath the Cu Pillar. Furthermore, process improvements applied to enhance the BEoL stack stability were investigated by GLOBALFOUNDRIES and have been implemented in high-volume production. GLOBALFOUNDRIES has also assessed Cu Pillar design related rules and has continued to improve the Cu Pillar bumping process. The main focus with respect to Cu Pillar design relates to the Cu Pillar diameter and the Cu Pillar stack. Process improvements had been carried out to reduce the undercut of the barrier underneath the Cu Pillar. The paper reveals data how an optimized Cu Pillar design and improved Cu Pillar processing can contribute to the risk mitigation of CPI failure modes in the BEoL. Advanced measurement methods generate data on the wafer level to achieve fast turn-around times. These methods include the Dual-Cantilever Beam (DCB) test, the Modified Edge Lift-off Test (MELT) and Bump Assisted BEoL Stability Indentation (BABSI) tests. These test methods had been successfully been applied for an early CPI risk assessment. The paper also discusses the package level thermomechanical modeling approach. Subsequently, the model has been applied to determine the critical factors on BEoL stress/strain during the flip-chip assembly reflow process. These factors include for instance the Cu Pillar bump geometry and stack up. The results of the modelling work were used to guide the design of experiments (DOE).|