Device Packaging 2019

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Cu diffusion into the glass under bias temperature stress condition for through glass vias (TGV) applications
Keywords: copper diffusion, glass interposer, through glass via
Glass is a promising substrate material for interposer due to its high insulating properties, low signal loss, and lower material and processing cost compared to Si. Glass interposers with Cu metallization have already demonstrated the potential for this application1. However, the diffusivity of Cu in the glass hasnt been reported which can affect the reliability of the interposer, such as short circuit of the device. Considering the operating conditions of an interposer in the package, Cu diffusivity in the presence of an electrical field at elevated temperature should be evaluated because Cu diffusion is enhanced by electrical fields 2. In this study, the Cu diffusivity in Glass interposer under electrical fields was evaluated to give guidelines for Cu diffusion length in each application. Corning SGW3 glass wafer was used for this experiment because it has the same coefficient of thermal expansion (CTE) as Si, and yields no thermal stress between Si devices and the glass interposer during packaging processes 1. To simulate the worst- case situation, oxidized Cu was used as the Cu source, because oxidized Cu has higher diffusivity in to the dielectric than pure metallic Cu 3. 20 nm of Cu film was deposited by an evaporation method to avoid intermixing directly onto bare glass without any barrier, and oxidized in air at 250oC for 60 min to fully- oxidize the film. A planar capacitor structure with a Pt electrode on Cu oxide was used. A 10 mm by 10 mm Pt electrode was formed by using a shadow mask. Cu oxide near the edge of the sample (25mm X 25mm) was removed by wet etching to avoid the breakdown around the edge of the sample. The breakdown voltage was evaluated at 400oC to determine the range of voltages that could be applied. SGW3 glass of 0.7 mm thickness showed breakdown at 4kV. Thus, the maximum voltage for this experiment was set at 3kV. These samples were annealed from 300 to 400oC with applied voltages of 1.5~3kV on 0.7mm SGW3 glass under N2 gas for 15 to 45 hr. After the bias temperature stress (BTS) test, the Cu film was reduced and the residue film was easily removed by tape. No wet etch was applied to the surface to avoid damage to glass surface. SIMS depth profiling was performed on the samples. Cu diffusivity was obtained by fitting of SIMS depth profile data for different temperatures and electrical bias conditions. Ficks 2nd law was used for fitting, and diffusivity of three different temperatures was obtained. From the high temperature (300~400oC) acceleration test, the activation energy of Cu diffusion in the glass was obtained and enabled the estimation of Cu diffusion for specific operating conditions (85~125oC). From an Arrhenius plot, the activation of Cu diffusion in the SGW3 glass is 1.1eV which is in the range of the values for the Cu diffusivity of deposited oxide in the backend BTS references 4. Using this activation energy and pre-factor, the Cu diffusion depth to the SGW3 glass can be calculated. For example: assuming low power logic device applications having a 2V operating voltage and 10 years operation at 85oC, the minimum spacing to have less than 20 nm Cu diffusion depth is about 0.5um5. This is a very short via spacing compare to bump spacing (>100um). Some MEMS application may needs high operating voltage (100~200V) 6. If operating conditions at 200V and 85oC for 10 year MEMS device, 50 um spacing of via will have less than 20nm Cu diffusion. Generally, high voltage MEMS device may not have such fine interposer via spacing due to concerns of electrical breakdown. Thus, most of the cases for glass interposer may not require a Cu diffusion barrier.
Hoon Kim, Research Associate
Corning Research and Development Corp
Corning, New York
United States

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