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A Cross-Domain, System Planning Methodology
Keywords: System , planning, optimization
Through several decades of electronic product design, three high-level design domains have emerged; IC (SoC) design, package (SiP) design and board (PCB/PWB) design. These three domains are separated and somewhat isolated, based on the EDA tools they use and by domain expertise. In many cases, the design tools come from 2 or 3 different EDA companies, leading to limited and in some cases, no way of sharing design data across the three domains. This typically leads to an “over the wall” design approach, resulting in downstream layout complexities for the package and board design teams, requiring domain expertise (human in the loop) in these design domains. Typically, this high-level of complexity occurs because the package substrate and board form-factor are not planned and optimized in context of the IC(s). Thus, the automation of these layouts becomes nearly impossible and tremendous human interaction (domain expertise) is the only way to complete the designs cost effectively. Moreover, this methodology directly impacts time to market, and results in products that do not live up to cost or performance expectations. Holistically planning and optimizing the complete SoC, package (SiP) and board “system”, will produce designs with ideal floorplans, pin-outs and component placements. These optimized designs/layouts will require fewer routing layers - drastically reducing cost and less human interaction (domain experts) to complete - drastically reducing design cycle time and minimizing human interaction. This presentation will outline a methodology to look at the different design domains as an overall system, plan the system at a higher level of abstraction, and then push the planning results into the implementation tools. The advantages of using such a methodology will be discussed. We will outline a tool that allows the designer to evaluate the entire system, identify opportunities for optimization (in both partitioning and assignment), and to drive those updates into their respective design domains. This means he or she must have the ability to access and modify the die driver placement, bump placement and assignment, the interconnect between the two, and the package ball placement and assignment. Providing a tool that allows the designer to see the physical extents of both the die and the package or packages, an interposer, and a printed circuit board allows them to look at the entire system as a whole and optimize placement and assignment. At this level they do not need all of the constraints or detailed routing, and can assess the design in a simplified state. Once the overall system is planned at a high level of abstraction, the design can then be transferred over to the implementation tools. Depending on the hierarchy of the design, this could be a single database or it could be multiple databases. The designer moves from a higher level of abstraction to the more detailed substrate or die implementation view. Here, the additional routing and manufacturing constraints can be applied and a more precise level of co-design can be leveraged. The designer now focuses on the detail of the interfaces between individual parts of the system and not the entire system. This includes tasks like swapping driver placement in the die, differential pair assignment, or bump to ball assignments in the package necessitated by the additional, more detailed design constraints. Leveraging both system-level path- finding and cross-domain co-design can ease some of the burden of complicated system requirements. Providing a multi-fabric view in a single canvas, allowing the designer to optimize interfaces in the context of the entire system early in the design process, and then moving that design into the implementation tools and leveraging cross-domain co-design to optimize the package and the IC layout eases the restrictions imposed by large designs. The designer can reduce the overall layer count, run advanced DRC's and leverage technology-driven capabilities within the tool to meet the stringent requirements of the manufacturer. The net effect is an overall improved system performance, design efficiency, and a reduction in overall design time, while maintaining the desired performance of the system.
BIll Acito, Product Engineer
Cadence Design Systems
Chelmsford, Massachusetts
United States

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