Honeywell

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Packaging and Assembly Techniques to Increase power density and simplify designs using 3-D SiP modules
Keywords: SIP, Power Modules, Integration
Today, designers are demanding an overall form-factor reduction to save board space, increase functionality, and allocate more circuit board real estate toward end-user applications all with less space allocated to power management where not just the X-Y shrink but the 3D volumetric shrink is required. For example in todays Telecommunications Cloud Infrastructure systems, board space and power density are challenging particularly in power supply designs where several high-current point-of- load rails are present. End equipment such as enterprise servers and switches, workstations, base stations, network attached storage, FPGA testers, network testers, and other test and measurement equipment employ several high-current CPUs, ASICs, FPGAs, and DDR memory all of which need high power, while the available board area is steadily decreasing. As long as 11.5-mm height is acceptable, a great opportunity today is integrating the inductor in the package and in some cases in a straddle mounted configuration directly above the IC, thus saving PCB area and optimizing the total volume of the power supply design. This paper will discuss volumetric co-design methodology and packaging construction trade-offs for 3D SiP power modules and also introduce the straddle mounted inductor assembly technique. It will also provide details around the SiP eco-system, co-design, construction, materials, and circuit topology.
Steven Kummerl, Semiconductor Packaging Engineer
Texas Instruments
Dallas, TX
United States


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