Device Packaging 2019

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System Co-Design Modeling Methodology of a High Speed (25Gbps) Multi-Rate 4-Channel Retimer: Simulation to Measurement Correlation
Keywords: FC Packaging, Modeling, Simulation, Co-Design, Measurement and Simulation Correlation
Goal/Objective: In this paper we detail the system (viz. silicon-package-pcb) electrical co-design of a 130nm BiCMOS high-speed (25Gbps) 4-channel multi-rate retimer, packaged in a small 6-mm 6-mm FC BGA package, with integrated advanced signal conditioning circuitries. Electrical optimization of the silicon-package-pcb over the high speed channels, to achieve desired performance, was achieved through a coupled circuit-to-electromagnetic co- design modeling and simulation methodology. Key figure of merits for system performance (viz. insertion loss, return loss, crosstalk/isolation, jitter, power supply inductance and resistance parasitics, among others) are modeled and characterized via simulation and measurements. Laboratory measurements, on a real SoC, are presented that validate the integrity of the modeling and simulation approach. Good correlation between modeling methodology and laboratory measurements is achieved. The Modeling Methodology: Operating parameters, cost, and package design considerations will impact high-speed channel performance. Consequently, ensuring that the packaged SoC meets specification is essential in high speed data communications. Across various implementations of high speed retimer, there are standard electrical performance metrics/figure of merits (FOMs) that are employed to characterize system design performance. Of particular importance to the package performance, are time- domain and frequency domain parameters. For time-domain, these include the inductance/resistance (RL) parasitics of the supply/ground network and jitter (both deterministic and random) which impact the power integrity of the device. The frequency domain parameters (viz. insertion loss, return loss, crosstalk, and isolation) impact the signal integrity performance of the device. To assess the signal and power integrity electrical performance of the package for both high-speed, an iterative coupled circuit-to- electromagnetic methodology was developed. The methodology/flow has primarily 4 steps namely [1] initial package physical design, [2] 3D time- domain quasi-static electromagnetic parasitics extraction model (RLGC) and 3D full-wave frequency-domain model extraction (s-parameters), [3] coupled silicon spice-level netlist circuit-to-electromagnetic system- level analysis, and [4] a check step where the FOMs requirements are compared to modeling results. If the requirements are met, the flow exits. If not, the flow iteratively proceeds back to the physical design until requirements are met. The accuracy of the electromagnetic solvers employed for the extraction of the package and PCB models have been validated on previous designs [1-3]. The flow described here was also employed to assess PCB performance. Additionally, a more accurate approach for the high speed links - is to merge the physical design of the package onto the physical design of the PCB and perform the extraction in one step. This is more accurate than extracting the model of the package and PCB separately and then concatenate them in the system-level circuit for transient analysis. This improved technique was demonstrated in [4] for a 12.5Gbps high speed link and has been employed for the analysis and correlation study here. Device/System Description, Measurement Set-up, and Results: The system-level co-design modeling methodology discussed above was implemented on TI DS250DF410, a 25Gbps multi-rate 4-channel retimer. The DS250DF410 is a four-channel multi- rate retimer with integrated signal conditioning. Each of the four channels operates independently. Each channel includes a continuous-time linear equalizer (CTLE) and a Decision Feedback Equalizer (DFE), which together compensate for the presence of a dispersive transmission channel between the source transmitter and the DS250DF410 receiver. The CTLE and DFE are self-adaptive. Each channel includes an independent voltage- controlled oscillator (VCO) and phase- locked loop (PLL) which produce a clean clock that is frequency-locked to the clock embedded in the input data stream. The high frequency jitter on the incoming data is attenuated by the PLL, producing a clean clock with substantially-reduced jitter. This clean clock is used to re-time the incoming data, removing high-frequency jitter from the data stream and reproducing the data on the output with significantly-reduced jitter. Each channel of the DS250DF410 features an output driver with adjustable differential output voltage and output equalization in the form of a three-tap finite impulse response (FIR) filter. The output FIR compensates for dispersion in the transmission channel at the output of the DS250DF410. To characterize/verify the high- frequency channel integrity and transmit jitter performance of the DS250DF410, an electronic verification module, i.e. a PCB system was designed and built. This EVM allows for easy evaluation of the 25 Gbps retimer DS250DF410. The high-frequency measurements (viz. insertion and return loss) set-up includes driving the high speed channels on the EVM with a PNA Series Network Analyzer & S-Parameter Test Set. The signal generator module is used to transmit (TX) the signals through the channel on the EVM and loop back out of the EVM to the RX signal analyzer module. This set-up provides for a complete channel characterization. The TX jitter was characterized using pattern generator, waveform analyzer, and high-end sampling scope. All measurements were done over wide frequency range and temperature. Good correlations are observed between modeling and measurements for high- frequency channel integrity and jitter.
Tony Tang,
Texas Instruments, Inc
Dallas, TX
United States

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