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Fine line panel level fan out changes the SiP landscape
Keywords: Fan out panel level packaging, advanced packaging, heterogeneous integration
In the past 10 years, Moore’s Law has faced great challenges. The transistors continues the step to smaller size but they have the limitations in performance and cost. Semiconductor industries are trying to come up with new ideas to keep the Moore’s Law moving forward. Wafer process keeps working on more Moore solutions and package houses working on more than Moore solutions. In recent years, industry considers chip split and re-constitution in SiP which has relatively shorter development time and lower cost than the SOC. But traditional SiP with wirebonding or FC connections to substrate will lead to high transmission resistance and induces higher power consumption. A new fine line SiP solution is important to shorten the connection between chips to improve SiP performance. Different from the 3D IC and 2.5DIC technologies, fine line panel level fan out has the advantages to reach good performance, design flexibility and high production efficiency. PTI is the first company to setup the fine line panel level fan out production line in the world. This paper will discuss about the challenges to setup this technology from standards setup, tools preparation, and process difficulties points of view. The dedicate machines to handle the fine line panel level fan out is critical. It is not easy to select suitable tools for this new technology. We also need to co-develop with tool vendors for some process stages which we could not find suitable tools from existing industries. Besides, panel warpage and chip shift are two of major process challenges. We will share our experiences on how to overcome these difficulties. Different structure and process have been developed for varied application requirements. The chip first will encapsulate chips first and build RDL layers on the encapsulation surface later. It is suitable for mobile AP, baseband, ASIC, PMIC and memory. The chip last solution will build RDL first, then flip chip mounting on the RDL. The RDL could be tested before chip mounting. It is suitable for CPU, GPU, FPGA, thermal sensitive devices. Pillars in fan out is a chip middle solution. It uses Cu pillars to connect top and bottom RDLs which is good for chip stacking. Currently the 5/5um line/space is already been qualified. 3/3um under developing and tool capability is 2/2um. We will demonstrate several cases to help readers understand this technology more. We expect this technology would be important for the coming era of 5G, automotive, IoT, and AI. We are trying to broaden its application to different kind of fields. For example, multi chips stacking in a fan out package to reach high bandwidth. Fan out stacking of logic and memory chips which can replace the existing PoP. The fan out SiP to integrate passives and/or other chips to achieve a compact SiP. Fanout could be one of the embedded substrate. It reaches homogeneous or heterogeneous integration. Another possible application are compartmental EMI shielding build by fanout technology, antenna in package or sensor. In short, this paper will introduce the challenges of Moore’s law as beginning, then explain the advantages of fine line panel fan out technology, and the challenges and our solutions. Finally, we will provide our concept of broaden the application fields of this technology.
Daniel Fann, CTO, vice president
Powertech Technology Inc.
Hukou, Taiwan

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