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Recess in the Motherboard architectures for small form factor systems
Keywords: Recess , motherboard , cavity
This paper details a novel architecture that includes a Recess in Motherboard (RiMB) cavity to enable increased packaging density of functional components (voltage regulation, EMI shielding) for next generation mobile products. In small form factor packages, the dynamic warpage of the silicon, package and board materials during SMT reflow process create potential interference between the mother board and land side package components, that cannot be supported by traditional collapse heights, which may result in solder joint opens. To minimize interference of these landside components with the MB, it requires either removing the Printed Circuit Board (PCB) material creating a hole in the or in more advanced cases removing finite layers of the PCB material to allow for components to sit into this hole/recess without impacting the surface mount process. This paper details the methodology used to arrive at the RiMB Z and XY tolerances, metrologies for measuring depth variations, PCB process options and considerations as well as concepts for electrically shielding land side component on the SOC package using RiMB. The paper will review the trade- offs required in designing the x- and y-tolerance of the Hole-in-Motherboard (HiMB) as it impacts the PCB manufacturing costs while keeping the HiMB as small as possible. Root sum squared tolerance modeling with key manufacturing tolerance will illustrate the analysis and subsequent design guidance used in this process. In the more advance concept where the hole only extends partially through the PCB, the discussion will cover the implications of the z-tolerance of this Recess-in-Motherboard (RiMB). The RiMB architecture was invented to address this concern while still preserving majority of layers in the MB under the CPU shadow to be available for routing. Like the HiMB technology the goal is to balance keeping the RiMB as small as possible, cost effective as possible to manufacture without allowing for interference from the backside components of the BGA package. This model is more complex since it must account for interference under reflow conditions. Intel has found the dynamic warpage of the silicon, package, and motherboard during SMT reflow process is the most critical to study and engineer against since it can lead to solder joint opens or long term SMT reliability concerns. Once design specifications are outlined by root sum squared interference methods, the paper will cover Intels metrology for measuring the HiMB aperture and RiMB depths. Data from both metrologies from Intel and PCB supplier builds will be reported. Alternative metrologies will be noted but not discussed in depth. SMT solder joint cross sections and temperature cycling results based on JEDEC JESD22- A104 standards will be provided to support the paper and its claims.
Tim Swettlen, R&D Engineer
Intel Corp
Hillsboro, OR
United States


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