Device Packaging 2019

Abstract Preview

Here is the abstract you requested from the imaps_2018 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.

A Systematic Approach to the Reliability Characterization of System in Package (SiP)
Keywords: System-in-Package (SiP), Digital Image Correlation (DIC) and Warpage, Finite Element (FE) Modeling
System-in-Package (SiP) solutions are gaining popularity across multiple market segments, dually reducing product design complexity for Original Equipment Manufacturers (OEMs) while increasing system performance and functionality. For SiP customers, product design complexity is reduced with the integration of electrical sub-system functionality into a module that can be designed into a product with relative ease. Further, logistical complexity is reduced, with the supplier carrying responsibility for the sub-system’s quality and reliability. In addition, OEMs benefit from the performance, functionality and form factor improvements enabled by advanced SIP packaging and substrate technologies. With the increased responsibility of SiP solutions in mind, the authors address a systematic approach to understand the complexity of thermo-mechanical risk and challenges in SiP solutions. This paper will describe a methodology to systematically characterize the critical factors that contribute to reliability of the SIP. Instead of using an application specific SIP package, authors used a test vehicle to demonstrate this approach. First, Shadow-Moiré technique was used for high-temperature warpage measurements of both the individual components as well as a fully assembled SIP. This information is critical primarily for enabling a robust assembly process, but also contributes to the understanding of stresses during temperature cycling. Next, a calibrated digital image correlation (DIC) system was used to measure the global Coefficient of Thermal Expansion (CTE). The DIC analysis was applied to the individual components, the SIP substrate, a fully assembled SIP and finally the motherboard to which the SIP would attach. The data collection from Shadow Moire and DIC were instrumental to physically understand the thermo-mechanical behavior of each component and its mismatch when combining them into a single SIP solution. This further help identify potential high stress locations and ultimately identify failure/concern areas. One of the critical challenges during SIP design phase is juggling to accommodate electrical routing constraints, performance/band-width requirements, component placements, material selection and reliability requirement. All these factors attributes to compounded Design of Experiments (DOE’s) both from design and assembly side. Thus, authors enhanced this systematic approach, adding Finite Element (FE) models to capture certain key attributes for the SIP solution. Two (2) thermo- mechanical areas were identified for this assessment, SIP level warpage and BGA interconnect reliability of the SIP package. A global finite element model was used to capture SIP warpage and a detailed BGA level model was used to predict interconnect reliability. Authors, finally performed an early correlation from the collected test data and simulation data. Although the work is preliminary, this systematic approach of characterization, followed by reliability testing, and FEA analysis is the right approach to tackle array of complexity looming from upcoming SIP packages or system solutions.
Karthikeyan Dhandapani, Staff Engineer
Qualcomm, Inc.
San Diego, California
United States

  • Amkor
  • ASE
  • Canon
  • Corning
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • Palomar
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Specialty Coating Systems
  • Technic