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|Enabling Robust Copper Seed Etching for Fine Line RDL by Electroplating on a Thin PVD Seed Layer|
|Keywords: high density fanout, RDL, Electroplating|
|Enabling Robust Copper Seed Etching for Fine Line RDL by Electroplating on a Thin PVD Seed Layer Integration of heterogeneous chips into fanout packages requires connection by redistribution lines (RDL). As I/O counts increase within the package, higher density routing can be achieved by finer RDL line/space dimension, by adding more stacked RDL layers, or both. If a robust fine line RDL process with good reliability can be implemented, considerable cost savings and reliability can be realized by interconnection with finer lines rather than adding metal layers. As an alternative, dual Damascene interconnection could provide the ultimate process for scaling in high density fanout, but the costs associated with implementation in the backend are high. We have outlined a project with the goal to enable sub-2µm RDL lines using more conventional WLP process flows at reasonable cost. RDL plating dimension is generally referenced as a line/space number in microns, so a 2/2 RDL refers to minimum line width of 2 µm with closest spacing of 2µm. Of course, line/space dimension varies across the die, but highest density of plating includes some 2/2 areas. Current anticipated requirements to achieve highest density predict line/space values of less than 1/1. Yole Advanced Packaging Report for 2017 shows 2/2 entering production in the 2023 timeframe, but some high end applications are likely to significantly beat this timeline. While there are certainly other integration challenges to fine line RDL for fanout packaging (including patterning issues), one fundamental limitation for immediate implementation is the challenge of removing the thick seed layer after plating the lines without impacting the electrical characteristic of the lines themselves. The seed/barrier etch process is performed in wet processing tools – first removing the copper seed with one etchant and then removing the barrier (usually titanium) with a second. By nature, the copper etch process is isotropic, and removes the plated copper film (laterally and vertically) as well as the targeted PVD copper film (vertically). To ensure that the copper seed is fully removed, an overetch of 30-150% is required once the seed film is visually clear. Assuming 100% overetch on a 3000Å seed layer implies removal of 6000Å of plated Cu height from the RDL (which can be compensated by plating thicker). Sidewall loss, however, is 6000Å per side, so the result is a net 1.2µm loss from a line targeted at 2µm wide. This coupled with variability in removal rates due to pattern density also creates large variations in cross sectional area that directly influence line resistance and line resistance uniformity across the die. Most existing plating chambers for WLP require a thick seed layer to facilitate uniform plating across the wafer. Thick in this case is 1000-3000Å PVD Cu. A thin seed (<800Å) is highly resistive and will plate preferentially close to the electrical contacts at the wafer edge, creating high thickness variation across the wafer. By using a chamber capable of plating on very thin seeds uniformly, the seed layer etch process influence on the plated copper line is decreased dramatically. For a nominal 200Å copper seed layer, sidewall loss becomes small even for much tighter line/space dimensions, and cross sectional area uniformity is improved. This presentation will discuss an integrated process for RDL including plating tests using a next generation chamber designed to plate on seeds as thin as 100Å and open area as high as 85%, supporting fine line RDL for high density fanout processes. Plated thickness uniformity (before and after seed etch) will be presented as a function of seed thickness. Data from the integrated process using a variety of RDL test vehicles with varied open area and L/S dimension will also be presented, including line resistance, line resistance uniformity, and leakage current for a variety of seed etch conditions. Ultimately, thin seed dies with several RDL layers will be assembled to generate reliability data and show results from an integrated process sequence.|
|Marvin Bernt, Process Engineer