Device Packaging 2019

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Fine Pitch Paste for System-in-Package Applications
Keywords: Solder paste, Printing paste, Type7 & Type8 powder particles
During the last twenty years, integrated-circuit technology has evolved dramatically from QFN to Chip- Scale-Package (CSP), System-in-Package (SiP), Package-on-Package (PoP), Wafer- Level-Package (WLP), 3D Through- Silicon-Via (TSV) technology, etc. Where, different modes of applications are required to complete the packaging assembly process. One of the most widely used assembly materials is solder paste, a mixture of alloy particulates and organic resin flux applied to form electrical interconnects between component and substrate. Solder paste has a long history of surface mount technology in board level applications both in millimeter and/or sub-millimeter level. However, alloy particulates in micron size level are developed to adopt in SiP. It is considered to be a cost effective interconnects over electro- plating. It is also versatile and reveals good printing performance to assemble wide range of component size (0402 to 008004 imperial code) with increasing component density on a single board. Recent developments in flip chip attach technology is with printed pad of 60~80m and copper pillars with printed solder tips. Such pad size ranges from 80 to 100m. The scope of present study is to investigate the influence of SAC305 (Sn-3wt%Ag-0.5wt%Cu) powder distribution and volume fraction addition on the rheology of the solder paste. In general, the type of SAC powder used in solder paste are defined as per IPC J-STD-005 standard such as Type4 (25-38m), Type5 (15-25m) Type6 (5-15m), Type7 (2-11m) and Type8 (2- 8m). Industry is yet to process finer sub-micron size particles. Surface area, surface roughness, total oxides, carbon content, spheroid nature, particle size distribution are characterized and studied in detail. The developed solder paste behaves as all-in-one printing paste of passive components to terminal pads and flip- chip copper pillar pads printing with low voids. In flip-chip attach using printed solder pads reveals excellent inter-connections, good wetting without substrate warpage. Good solderability between solder tin and copper cap is observed, thus preventing solder creep in copper pillars. Both terminal and flip-chip pads are printed using a stencil in a single step. This provides clean flip-chip pads without flux or dipping paste, simplifying the SiP assembly process with reduced cost and process time. The results showed finer the powder (T5 and finer), higher the deposited paste volume leading to lower voids, say less than 5%. However, the challenge is to print both large and fine features in a single stencil step while ensuring sufficient solder required for passive components terminal attach. Printing on smaller pads has higher consistency of printed volume than printing on larger pads. Zero defects is noticed, especially the bridging defect on printing with 100m opening. Furthermore, the reflow profile conditions (dwell time, peak temperature, pre-heat temperature and time, vacuum or inert environment, etc.) showed significant impact on solderability, high yield about 99%, low void formation. In summary, optimal solder paste release and volume consistency in fine pitch interconnects strongly depends on the control of powder particle size, its distribution and volume fraction of addition. During reflow of large dies, applying vacuum after melting of solders significantly reduces the voids. The paper enumerates the experimental research on novel solder paste application in large dies and a single step stencil processing.
Zhang Ruifen,
Heraeus Materials Singapore Pte Ltd
Singapore, Singapore

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