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|Design and Demonstration of 3D Glass Panel Embedded (GPE) Packages for Heterogeneous Integration|
|Keywords: Embedded & Advanced Substrates, Fan-out, Panel Level Processes, 3D Heterogeneous integration|
|This paper demonstrates an advanced 3D Glass Panel Embedded (GPE) package for heterogeneous integration, with high- density interconnections for digital bandwidth, and low loss Through- Package Vias (TPVs) integrated in the fan-out area for double-side RF component assembly. The Georgia Tech GPE approach addresses the most important challenges of current Wafer Level Fan-Out (WLFO) packages, namely, die shift and warpage. Die shift reduction and warpage reduction by a factor of 2-3x compared to molded fan- out package is enabled by the CTE matching of glass to silicon ICs and the superb dimensional stability of glass in which the ICs are embedded. This paper demonstrates a 3D fan-out package capable of Si-like RDL integrated on high bandwidth memory emulator chips embedded in thin glass panels with TPVs in the fan-out region for the first time. WLFO packages have disrupted the entire semiconductor industry due to its benefits in size, cost, electrical and thermal performance, reliability and potential for heterogeneous integration when compared to traditional flip-chip and wire bond packages. Although it was initially designed to extend package I/O counts beyond fan-in Wafer Level Packages (WLP), the scope of WLFO technology has expanded significantly in recent years to include multi-die SiP modules with high-density RDL, as well as high I/O logic and memory integration. Most WLFO packaging technologies today use epoxy based mold compounds as the carrier [1-4]. 3D integration in WFLO, today, is primarily pursued by means of a TEV or through-encapsulant via which is a vertical interconnect through the mold compound in the fan- out area. However, the use of mold compounds limits the scalability of current WLFO packages in a number of ways: (i) mold compounds have a large amount of shrinkage during cure and the CTE mismatch with silicon causing die shift (ii) molded surfaces have significant roughness due to the high volume of silica fillers, impacting RDL resolution and requiring expensive grind and polish steps, (iii) mold compounds suffer from large area warpage that hinder scaling to large panel processing which can reduce the cost by up to 2-4x, (iv) the poor loss-tangent of mold compound affects the quality of the signal carried by the TEVs and (v) the TEVs are immensely pitch limited due to the difficulty in drilling through mold compounds with large fillers. In order to address these limitations, Georgia Tech has been developing 3D Glass Panel Embedding (GPE) with a focus on reducing die shift to less than 1-2um , through vias at 100um pitch, and RDL at 1-2um lines and spaces. Glass, when used as a carrier for die embedding, not only outperforms other organic solutions, but also provides many other benefits not found in existing WLFO technologies. The smooth surface and high-dimensional stability of glass enables high-density silicon- like RDL wiring and BEOL-like I/Os even on large panels, thus increasing productivity and lowering cost, bringing an unparalleled combination of high I/Os and low cost. The CTE of glass can be tailored, thus, improving reliability and enabling the direct surface mounting onto the board unlike some high-density fan-out packages that require an organic package to connect to the board for large body sizes. Glass has ~2-3x lower loss- tangent as compared to most mold compounds, making GPE an ideal candidate for high-frequency applications. Glass also provides high resistivity, excellent moisture resistance and high surface smoothness as compared to mold compounds. Although glass based embedded fan-out packages promise superior benefits, there is a continuing need to improve I/O density, electrical & thermal performance, yield, cost and chip- & board-level reliability of GPE packages. For all of these reasons, 3D GPE can be explored for non-TSV based high-performance 3D architectures for System-on-Package applications. This paper demonstrates through via integration in the fan-out region of GPE packages to enable 3D architectures while also making use of the superior electrical and mechanical properties of glass-vias. Based on the formation of glass cavities, 2 different architectures were considered to realize a 3D GPE package: 1) Blind-cavity GPE and 2) Laminated-Cavity GPE. In bind-cavity GPEs, the cavities are, basically like wells, formed on bare glass by wet- etching methods. Based on the thickness of the dice, the cavity depths are controlled by optimizing the etching process. The vias are drilled with respect to the position of the cavities on the panel. In laminated-cavity GPE, the structure is realized by laminating a through- cavity glass panel on to a bare glass panel by use of a polymer adhesive. Here, the cavity depth is determined by the thickness of through-cavity glass panels. The vias were then laser drilled through the sandwich structure at positions respective to the cavities. Daisy chain test dies provided by Global Foundries were used to emulate an embedded device with the size of 7.2 mm x 7.2 mm, thickness of 100 μm and pad pitch of 50 μm. Glass panels with 100 μm thickness and through glass cavities were first fabricated with cavity location and dimension accuracy below +5 μm, and then then bonded on a 50 μm thick glass panel carrier using adhesive bonding. Blind-cavity panels used were 130 μm thick with cavities of 100 μm depth. A high-speed placement tool from Kulicke and Soffa is used to embed the test dies in these glass cavities using die-attach film (DAF). RDL polymers were then laminated and cured on both sides to minimize the warpage of the ultra-thin package. When cured, this polymer flows and fills up the cavities and vias. A surface planar tool by Disco was then used to planarize the surface of the panel to avoid non-coplanarities. A picosecond UV laser tool from ESI is used to drill i) through-vias inside of the glass vias to form a via-in-via structure and ii) blind microvias to expose the bumps on the die. Following this, RDL is plated by a standard semi-additive process (SAP) to form interconnections between the chip, package and integrated vias. In summary, this paper demonstrates 3D Glass Panel Embedded packages for heterogeneous integration of digital and high-frequency functions in a single package by integrating through vias in the fan-out region of the glass packages.|
Georgia Institute of Technology