Honeywell

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Customization of chemistry continues
Keywords: Chemistry, Advanced Packaging features, Integration complexity
Advanced packaging continues to evolve as the electronics market (Mobile, IoT, Automotive, etc.) demands better performance, thinner packages, smaller footprints, improved reliability, and shorter design cycles. This had typically been accomplished with Moore�s Law coupled with higher performance package solutions such as Flipchip, System in Package, WLCSP or FOWLP designs. The recent introduction and successful production ramp of High Density Fan Out Wafer Level Packages (i.e InFO, SWIFT, etc) has re-defined the package technology roadmap and provided a platform for heterogeneous integration. Within these �heterogeneous� solutions the interconnects such as Cu Pillar, Thru Mold Via, TSV and the routing traces are integral in determining the overall performance of the package. These are the connections that link the individual components to create a higher level of integration that leads to improved performance. More specifically, it is these electroplated features (Cu, Ni, Sn, SnAg, Au, etc.) that are being pushed to the limit to meet the demands of heterogeneous designs. In order to maximize performance these chemistries are being developed specific to the design, application and tool set being used. For example, chemistries and solutions that are developed for a specific design may not be suitable for another. Also, the chemistry and tooling used for wafer level processes are different than those used for panel level processes, however they are both pushing the equipment and materials towards the 1um to 10um window. This presentation will illustrate the different types of RDL, via fill and Pillar chemistries that have been developed for specific High Density applications. In addition, we will identify some of the challenges that we are facing today and what we see coming in the future.
Eric Gongora, Elie Najjar,
MacDermid Enthone Advanced Electronic Solutions
West Haven, CT
United States


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