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Electrical Characterization of Low Temperature PECVD Oxides for TSV Applications |

Keywords: TSV , Low Temperature PECVD Oxide , Electrical Characterization |

Abstract In the present work we investigate the quality of low temperature PECVD and plasma treated TEOS-based TSV-liner films. Different designs of TSV Test structures with 10µm and 20µm width and a depth of 100µm have been fabricated. Two differently doped silicon substrates have been used – highly p-doped and moderately doped. The results for break-through, resistivity and capacitance for the 20µm structures show a better performance compared to the 10µm structures. This is mainly due to increased liner thickness in the reduced aspect ratio case. Lower interface traps and oxide charge densities have been observed in the C-V measurements results for the 10µm structures. Introduction The electrical characterization of the TSV passivation layer (will be referred to as TSV-liner in this work) is a common task in the fabrication of TSVs. This step usually includes the measurement of the TSV's leakage current, breakdown voltage, capacitance, inductance, and high frequency performance. These quantities vary greatly among the common passivation processes; thermal oxidation for instance provides the best quality TSV-liner, however at process temperatures exceeding 700 °C making it only applicable in the very early stages of the fabrication [6]. In the later stages of the fabrication, TSV processes (Via-Middle, Via –Last, etc.) should be performed at appropriate temperatures taking the melting point of the metallization and the induced thermal stress into consideration. Authors in [3], [4], [5], and [6] have reported using PECVD TEOS and SACVD processes for the isolation of the TSVs in their test structures, at temperatures ranging between 300 °C and 420 °C; some have also performed a subsequent thermal treatment of the TSV-liner in a forming gas ambient around the deposition temperature. Although these deposition temperatures are relatively low compared to thermal oxidation, for some processes with a strict thermal budget, lowering the temperature further is necessary, possibly without sacrificing the electrical quality of the TSVs. Low temperature oxide deposition plays an important role in the wafer-level packaging of modern electronic systems, for example in the processing of thin wafers that are bonded to a glass carrier using an adhesive, or wafers that have temperature- sensitive components. Further investigation of the TSV-liner is needed to ensure proper electrical performance for systems that require TSVs with smaller dimensions and higher densities on a single chip. Another aspect that should be investigated is the TSV capacitance which determines the delays and the high frequency performance. Fabrication In this work, two sets of silicon wafers have been fabricated to extract the electrical properties of TSVs. The main difference between the two batches is that the first had TSVs with 10 µm diameter, and the second had TSVs with 20µm diameter. In both cases the TSVs were about 100µm in depth. Hence, the aspect ratio was 1:10 and 1:5 respectively. Figure 1 shows an overview of the fabrication process of the TSV. Starting with a thermal oxide and a lithography for generating the silicon bulk contact using dry etching for structuring the oxide and then sputtering and structuring aluminum as a bulk contact. The aluminum was annealed at 500°C to generate the ohmic contact. In Figure 1 b) [there is no Figure 1 b)??] the generation of the TSV is shown. First, the topside thermal oxide is etched using reactive ion etching (RIE). The exposed silicon is etched 100µm deep using DRIE. In the subsequent step the low temperature, TEOS-based SiO TSV liner is deposited at 175°C using a Delta fxP system from SPTS [4]. After removing the resist and cleaning the wafer a Ti/Cu seed layer was sputtered using a HIPIMS sputtering process and afterwards electroplating has been performed to fill the TSV with copper. The topside of the wafer was polished using CMP and a topside RDL was generated using again Cu electroplating. Figure 1: TSV process flow Electrical Model of TSV For the electrical measurement different test structures have been developed. Figure 2 shows a single die with the test structures for electrical measurement like Kelvin structures, TLM structures, daisy chains and TSV fields with different dimensions and TSV densities. We selected for the resistance and capacitance measurements the Test structures shown in Figure 3. Figure 2 Single die with various test structures defined various groups. Figure 3: Test structures used for characterization of TSV resistance and capacitance with different amount of TSV in the same area – different TSV density. Test structures on top (type 1) have higher electrode areas and a higher TSV count, where the bottom structures (type 1a) have smaller Top electrode area and a lower TSV count. Figure 4: Detailed view on a probing This field consists of a TSV Matrix, an upper electrode that covers the whole TSV field, an outer ring with Bulk contacts and some probing pads. Each test structure contains a different quantity of TSVs on the same area. Figure 4 shows a more detailed image of a single TSV field with surrounding bulk contacts. On the right-side a cross-section on the TSV field and the bulk contact is shown. After the processing of the wafers the C-V Characteristics of the TSV test structures have been measured. The TSV forms a MOS (Metal Oxide Semiconductor) system where the TSV plug acts as the metal electrode, the liner as the insulating oxide and the silicon substrate as a semiconductor. The system is voltage dependent. For a MOS system, in the so-called inversion regime, the depletion layer can behave in two ways according to the frequency of the applied signal. If the frequency is low, the minority carriers can follow the slow AC signal and the depletion layer will diminish. The total capacitance of the device will increase to Cox same as in the accumulation regime. However, at high frequencies the minority carriers are too slow to follow the signal. The inversion layer maintains its maximum width and the total capacitance remains constant at its minimum value. Cdep;min can be calculated using equation 1 [1]. C_(dep,min)=2∙πε_si l_TSV (ln(R_max/R_ox ))^(-1) The ideal dynamic behavior of the TSV's capacitance can be illustrated with C-V plots as in Figure 5. At high frequencies the total capacitance reaches its minimum in inversion. Electrical Measurement The electrical measurements have been performed on a semi-automatic wafer prober with a parameter analyzer and an electrometer (Keithley 4200A-SCS and Keithley 6517b). The parameter analyzer is provided with 4 SMUs for I-V measurements, two of which are equipped with pre-amplifiers for low level measurements. These will be used to measure the leakage current of the TSV structures and to determine the I-V characteristics in a low voltage range. A fifth module, the 4200-CVU, is also incorporated in the parameter analyzer and is used for C-V measurements. Apart from the parameter analyzer, the 6517B electrometer is used to measure the breakdown voltage. The leakage current was measured applying -1V on the TSV pad and ground potential on the bulk contact pad. The measurement voltage was set to -1 V in order to drive the TSV in accumulation (negative voltage) and prevent the oxide from degrading. Figure 6 shows the results of the resistance measurement in a cumulative percentage plot for the 20 µm wide vias. The matrix is equivalent to a parallel circuit of all TSVs, therefore, as the number of TSVs increases, the total resistance of the TSVs within the features decreases. The non-uniformity of the resistance across the wafer increases as well, since the probability of having TSV-liners with defects increases with the TSV count. Figure 5: Charge accumulation and depletion at the Si/SiO2 interface and the corresponding high-frequency CV plot. Figure 6: Cumulative percentage plot of the TSV-to-Bulk resistance of a 20 µm TSV feature (Type 1a) Figure 7 shows the cumulative percentage plot of the bulk resistance for the 20 µm (type 1). The type 1 features have a larger electrode area and a higher TSV count. These features show a more pronounced spread in resistance between 103 Ω and 1015 Ω. The 1024 type 1 via field is exceptional as ~90% of the vias have a resistance ≤ 1 kΩ. This can be explained by a thinner TSV-liner due to the higher TSV density and a higher Figure 7: Cumulative percentage plot of the TSV-to-Bulk resistance of a 20 µm TSV feature (Type 1) probability of TSV-liner defects. To validate the wafer to wafer consistency six wafers have been processed and measured. Figure 8 shows a box plot of the resistance of type 1a structures with 9 TSVs. The mean value and the spread is confined to values higher than 1012 Ω. The only exception here is the wafer SEA3 which differs from the other wafers by a larger spread of ~ 25% of the values, denoted by a large lower whisker of the box plot. This can be explained by a defective region on the wafer that comprises a large number of low resistance matrices. Figure 8: Box plot of the resistance of Type1a-9 TSVs across all p++ wafers In the cumulative percentage plot of Figure 7 it can be seen that the TSV field with 1024 vias has a much lower resistance compared to the fields with lower TSV count. In order to find an explanation, liner thickness measurements have been performed. Figure 9 shows the results of TSV-liner thickness for the type 1 features on top of the wafer, on TSV top sidewall, on TSV bottom sidewall and on TSV bottom. These values have been recorded for the left and right edge of the wafer. It can be observed that the liner thickness decreases with an increasing TSV count and that the TSVs of the left edge of the wafer have a thinner oxide insulation layer compared to the right side of the wafer. The explanation of this behavior is that the deposition of the oxide has a gradient from left to right. The overall uniformity of the TEOS deposition process is less than 2%. The results of the SEM inspection of the TSV-liner thickness can only serve as an estimation and should not be taken as accurate results, as one cannot exclude artefacts produced during sample preparation such as cracks, smearing and contamination, non-concentric cleaving of the TSV, insufficient sputtering of the SEM sample prior to the inspection, and the fact that some measurements have shown position-dependent variation of the liner thickness within a single TSV-matrix (especially for the dense TSV-fields the thickness decreases considerably from the border of the field to the center). Aside from the careful preparation of the samples, more precise results can be achieved by locally etching the sidewalls at the measurement positions using FIB, thereby removing the smearing and the contamination which could distort the measurement. On the other hand, the TSVs which are undergoing the inspection should have well-defined positions in the TSV-matrix in order to avoid inconsistencies in the measurements caused by local thickness gradients within the matrices. Figure 9: SEM measurements of the 20µm TSVs liner thickness vs. TSV count (Type1), comparing TSVs from the left edge and from the right edge of the wafer The resistance measurements have also been performed on the wafers with 10µm TSV diameter. The TSV depth was kept 100µm deep throughout all tests. Compared to the 20µm TSV Figure 10: Cumulative percentage plot of the TSV-to-Bulk resistance of 10µm measurements the 10µm TSV fields showed a modest performance. In the Type1a matrices with the lowest TSV count, 30% of the 10µm single TSV fields had a resistance < 1012 Ω compared to 1% of the 20µm single TSV fields. The spread of the resistance increases significantly with the TSV count, 70% of the 10µm 36-TSV matrices have a resistance < 1012 Ω compared to only 15% of the 20µm TSVs. This decline in the TSV's performance is also observed in the Type1 matrices and can be attributed in both cases to the thinner TSV-liner compared to the 20 µm TSVs, which renders the TSVs more vulnerable to stress-induced failures. Breakdown Voltage The measurement of the breakdown voltage is performed using the Keithley 6517B electro-meter. For this measurement, a feature with a single TSV is chosen (Type1a-single TSV). One of the probing needles is placed on the copper electrode with the TSV, and the second probing needle is placed on a bulk contact outside the TSV field. The 172 test sites on the wafer are stepped while sweeping the voltage from 0 V until the dielectric breaks down on each TSV. Assuming that the thinnest part of the oxide is most susceptible to dielectric breakdown under an electric field, the liner thickness at the TSV's bottom is taken as a reference point to calculate the breakdown electric field. The liner thickness is assumed to be 50nm and 125nm for the 10µm and 20µm TSVs respectively. These values correspond to the SEM measurements on the Type1 feature with the 16-TSV matrix (Figure 9), and should be the best approximation of the liner thickness on the single TSV matrix because of the low TSV density. The results are illustrated in the cumulative percentage plot in Figure 10. The results cover a large range of electric fields with a steadily increasing frequency of occurrence from < 1 MV cm-1 up to ~8 MV cm-1. The breakdown electric field is non-uniform across the two wafers. Nevertheless, comparing the TSVs of different diameters shows that only 10% of the 20µm TSVs break down at fields lower than 4 MV cm-1 compared to ~80% of the 10µm TSVs. This significant discrepancy between the two types of TSVs indicates that the thicker liner as in the 20µm TSVs is more resilient to defects and mechanical stress that could cause the early failures seen in the 10µm TSVs. Figure 11: Cumulative percentage plot of the breakdown voltage measurements CV measurements The CV measurement have been carried out using a Keithley 4200-CVU module of the Keithley 4200-SCS parameter analyzer. The measurement of a single TSV will result in a capacitance in the pF range where accuracy issues might arise. To overcome this, TSV matrices with multiple TSVs are tested in order to reach a higher total capacitance. The capacitance for a single TSV can be calculated by dividing the measured capacitance by the total number of TSVs. The measurement results of 172 sites are shown in Figure 12. Figure 12: Single TSV capacitance vs. position on wafer of different matrices before mathematical correction A large difference in the single TSV capacitance can be observed in type1 matrices with the larger copper electrode on top of the structure. The calculation of this top electrode with ~1.7µm oxide on top results in a capacitance of 28.5 pF. This value has to be subtracted from the measured result for the TSV field. Generally, the influence of the planar capacitance lowers with a higher TSV count. The measurements were carried out on 9-TSV and 36-TSV matrices of Type1a, and 16-TSV and 256-TSV matrices of Type1. Common for all matrices are the ripples in the plot. The wafers are stepped from left to right, starting from the upper left chip. The ripples indicate that there is a factor that has led to this systematic variation in the capacitance, Figure 14 shows that the variation of the TSV's depth is negligible, however variations in the TSV-liner thickness could explain the non-uniformity of the capacitance. Figure 13: Single TSV capacitance vs. position on wafer of different matrices after mathematical correction By calculating the TSV-liner thickness from the capacitance values of Type1 16-TSV matrices, and displaying them in a wafer map, a correlation to the thickness variation of the deposited PETEOS film can be observed. The standard deviation of the TSV- liner is with 3% very close to the standard deviation of the PETEOS planar film of 1.86%. On the other hand, the measurements show that the single TSV capacitance of a 256-TSV-Matrix is on average about 0.2 pF higher compared to matrices of lower TSV densities. Figure 14: TSV depth measurement of wafer on the spectral reflectometry (SemDex 301) In the IZM 3D-IC integration flow the wafers are temporarily bonded to a 500µm thick glass carrier using spin on adhesive. After the bonding, the wafers are thinned down to 130µm with a TTV of 2µm. As the TSVs are still entirely embedded in silicon they need to be revealed. Here wet etching and dry etching of silicon are possible approaches. Potassium hydroxide is a common etchant for silicon and could be used to reveal the TSVs as they are still encapsulated with the liner passivation [2]. Unfortunately, the process control of wet etching is difficult as it is required to achieve a reproducible nail height. Instead of wet etching we used a Figure 15: Comparison of nail heights after silicon dry etching using the in-situ end-point detection. highly selective to oxide and highly uniform SF6 based silicon dry etching process [8] in our 200mm SPTS Rapier™ plasma etch system. To address the problem with post heights an in-situ end-point detections system (ReVia®) has been used. Figure 15 shows the nail height distribution after silicon etching using the end-point detection. It can be seen that the height in the center and at the wafer edge are ~2-3µm which allows an optimal further processing of the wafers. These results will strongly depend on the uniformity of the TSV etching process and on the uniform dry etching revealing the TSV nails. Conclusion Measurements on the 20µm TSVs have shown a superior performance over the 10µm TSVs. The main reason is the thicker TSV-liner which is estimated to be on average about 2.5 times larger in the 20µm x100µm TSVs. This has been observed in the SEM inspections and calculated from the extracted capacitance values of the TSVs. Thinning of the TSV-liner in matrices of high TSV densities has been observed in SEM inspections and capacitance measurements. The capacitance of TSVs in a Type1 256-TSV matrix was higher in comparison to TSV-matrices with lower densities, indicating a lower TSV-liner thickness. This implies that the thickness of the deposited LT PETEOS should be adjusted according to the TSV density. In the breakdown and resistance measurements, a significant spread of the measured values within a wafer between 103 Ω and 1015 Ω was observed. This spread could not be attributed to the non-uniformity of the deposited PETEOS. It has been determined that the spread becomes increasingly notable with higher TSV count and a larger areal distribution for a given TSV count. The spread in the 10µm TSVs was larger. A reasonable explanation of this inconsistency in the results could be the presence of impurities prior to the TSV- liner deposition, or the non-uniform distribution of TSV-liner defects due to mechanical stress. The capacitance measurements returned more uniform results. The high frequency C-V measurement is less sensitive to leakage currents. As a result, the capacitance values are a function of area, which is constant, and TSV-liner thickness that is in line with the thickness on the wafer's surface, decreasing from the left side to the right side of the wafer with a standard deviation of 3%. The mean value of the capacitance density in 10µm and 20µm TSVs is 68 nF.cm-2 and 28 nF.cm-2 respectively. |

Piotr Mackowiak, Fraunhofer IZM Berlin, Berlin Germany |