Honeywell

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Design, Materials, Process, Fabrication, and Reliability of Fan-Out Wafer-Level Heterogeneous Integration
Keywords: FOWLP, RDLs, New Process
The design, materials, process, fabrication, and reliability of a heterogeneous integration of 4 chips and 4 capacitors by a FOWLP (fan-out wafer-level packaging) method are investigated in this study. Emphasis is placed on the application of a new assembly process for fabricating the RDLs (redistribution layers) of the FOWLP. First of all, in the present study, the chips are not embedded in an epoxy molding compound by the conventional compression molding method. Instead, after picking and placing the chips face-down on a temporary stainless steel carrier, it is followed by printing and curing an epoxy on the chips and capacitors on the reconstituted wafer. Then, a glass carrier coated with a light-to-heat-conversation layer is attached to the backside of the epoxy. De-bond the steel carrier and fabricate the RDLs and the mount the solder balls. Then, de-bond the glass carrier by a laser and dice the reconstituted wafer into individual fan-out wafer-level heterogeneous integration package. Reliability assessments such as the thermal cycling test and drop test are also performed. The advantages of the present process are lower package profile and lower cost.
John H Lau,
ASM Pacific Technology
Hong Kong, Hong Kong


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